NXP Semiconductors LPC55S06JBD64E

Overview

LPC55S06JBD64E from NXP Semiconductors is a 32-bit ARM Cortex-M33 microcontroller with TrustZone security, PRINCE flash encryption, CASPER crypto co-processor, 256 KB flash, 96 KB SRAM, CAN FD interface, and 16-bit 2.0 Msamples/sec ADC. It targets secure industrial control, automotive body electronics, and IoT edge nodes requiring certified boot and hardware-accelerated cryptography.

For engineers reviewing the LPC55S06JBD64E datasheet, LPC55S06JBD64E pinout, LPC55S06JBD64E application, or LPC55S06JBD64E equivalent, key selection criteria include TrustZone-enforced memory isolation, PRINCE real-time flash encryption/decryption, CASPER-accelerated ECC operations, 45 GPIOs with secure interrupt routing, and CAN FD compliance up to 5 Mbit/s in automotive-grade temperature range (−40 °C to +105 °C).

Technical Context

The LPC55S06JBD64E implements ARMv8-M architecture with TrustZone, enabling hardware-isolated secure and non-secure execution environments. Its CASPER co-processor offloads elliptic curve cryptography (ECC) operations including point multiplication, while PRINCE performs AES-128 on-the-fly encryption/decryption of flash reads and writes without software overhead.

Security is enforced via integrated PUF for key generation, SHA-256/HMAC-AES-256 engines with dedicated DMA, RSA-2048/4096 signature verification for secure boot, and DICE-compliant Device Identifier Composition Engine. The dual DMA controllers (23+10 channels) enable concurrent peripheral-to-memory transfers across secure/non-secure domains.

Key Specifications

Pinout & Package

Package: HTQFP64 (plastic low profile quad flat package, 64 leads, 10 × 10 × 0.5 mm body, SOT 855-5). Exposed thermal pad must be connected to VSS.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar secure microcontroller applications.

Compared with LPC55S06JBD64E, LPC55S16JBD64 provides expanded memory and RSA acceleration while maintaining pin compatibility, whereas RA6M5GFP64A trades hardware crypto acceleration for higher clock speed and connectivity-requiring architectural evaluation for security-critical use cases.

Availability

LPC55S06JBD64E is available at Aetrix Electronics and suitable for industrial PLC I/O modules, automotive body control units, and secure IoT gateway nodes requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for LPC55S06JBD64E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with leadership in ARM-based microcontrollers and trusted execution technologies.

The LPC55S0x series is designed for embedded applications demanding hardware-enforced security, real-time performance, and low-power operation-targeting automotive body electronics, industrial control, and secure edge devices.

FAQ

What is the maximum operating frequency of the LPC55S06JBD64E CPU core?

The LPC55S06JBD64E features an ARM Cortex-M33 core rated for operation up to 96 MHz. This frequency is achievable using the internal 96 MHz Free Running Oscillator (FRO), PLL0, or PLL1 clock sources. The FRO is factory-trimmed to ±1% accuracy across voltage and 0 °C to 85 °C, and ±2% over −40 °C to 105 °C. All timing-critical peripherals-including the 16-bit ADC, SCTimer/PWM, and CAN FD module-are synchronized to this clock domain, ensuring deterministic real-time behavior in the LPC55S06JBD64E.

Does the LPC55S06JBD64E support secure boot with cryptographic signature verification?

Yes, the LPC55S06JBD64E supports secure boot using RSASSA-PKCS1-v1_5 signatures of SHA256 digests. It validates images using RSA-2048 or RSA-4096 public keys stored in x.509 certificates, with up to four revocable Root of Trust keys stored in protected flash. The ROM bootloader enforces anti-rollback via image key certificate revocation using the x.509 serial number field, and supports NXP Secure Boot file format version 2.0 (SB2). This capability is integral to the LPC55S06JBD64E's security architecture and requires no external components.

How many ADC channels does the LPC55S06JBD64E provide, and what is its sampling rate?

The LPC55S06JBD64E integrates a 16-bit ADC with nine single-ended input channels (or five differential pairs), supporting simultaneous conversions on two channels within a differential pair. Its maximum sampling rate is 2.0 Msamples/sec, enabled by dedicated hardware sequencers and multiple trigger sources-including timers, Flexcomm interfaces, and external pins. The ADC connects to an integrated temperature sensor and supports internal reference voltages, making it suitable for precision measurement in the LPC55S06JBD64E's target applications.

What package type and pin count does the LPC55S06JBD64E use?

The LPC55S06JBD64E uses the HTQFP64 package: a plastic low-profile quad flat package with 64 leads, 10 mm × 10 mm body size, 0.5 mm pitch, and SOT 855-5 footprint. The exposed thermal pad must be soldered to VSS for thermal management. This package supports all 45 GPIOs, nine Flexcomm interfaces, CAN FD, and full peripheral routing as specified in the LPC55S06JBD64E datasheet, distinguishing it from the HVQFN48 variant which has fewer I/Os and Flexcomm instances.

Does the LPC55S06JBD64E include hardware acceleration for cryptographic operations beyond AES?

Yes, the LPC55S06JBD64E includes two dedicated hardware accelerators: PRINCE for AES-128 on-the-fly flash encryption/decryption, and CASPER for elliptic curve cryptography (ECC) operations including point multiplication on NIST P-256 and P-384 curves. CASPER reduces ECC computation time by more than 10× compared to software-only implementations, directly accelerating secure boot certificate validation and TLS handshake operations. These accelerators operate independently of the Cortex-M33 core, preserving CPU bandwidth for application tasks in the LPC55S06JBD64E.