NXP Semiconductors LPC55S06JBD64K

Overview

LPC55S06JBD64K from NXP Semiconductors is a secure ARM Cortex-M33 microcontroller for embedded applications requiring hardware-enforced isolation, cryptographic acceleration, and real-time analog sensing. It integrates 256 KB flash, 96 KB SRAM, PRINCE flash encryption, CASPER crypto co-processor, CAN FD interface, and a 16-bit 2.0 Msamples/sec ADC - deployed in industrial gateways, secure IoT edge nodes, and automotive body control modules.

For engineers reviewing the LPC55S06JBD64K datasheet, LPC55S06JBD64K pinout, LPC55S06JBD64K application, or LPC55S06JBD64K equivalent, key selection criteria include TrustZone®-enabled secure boot with RSA-2048/4096 support, PUF-based key generation, PRINCE real-time flash encryption, and Flexcomm-configurable serial interfaces (UART/I2C/SPI/I2S) across 8 channels.

Technical Context

The LPC55S06JBD64K implements ARM TrustZone® at the silicon level to partition secure and non-secure execution environments, with dedicated memory protection (MPU), secure GPIO, and debug authentication via RSA-2048/4096. Its CASPER co-processor accelerates ECC operations, while PRINCE enables transparent on-the-fly AES-256 encryption/decryption of flash contents during read/write.

It features dual DMA controllers (23+10 channels), five 32-bit general-purpose timers, an 8-input/10-output SCTimer/PWM, and a programmable logic unit (PLU) for custom state-machine offload - all synchronized under a unified clocking architecture with FRO-based 96 MHz core operation and 32 kHz RTC domain.

Key Specifications

Pinout & Package

Package: HTQFP64 - plastic low-profile quad flat package, 64 leads, exposed thermal pad connected to VSS.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar secure microcontroller applications.

Compared with LPC55S16JBD64 and RA6M5GFPM80A, the LPC55S06JBD64K delivers optimal balance of certified security primitives (PRINCE/CASPER/PUF), compact footprint, and cost efficiency for mid-tier secure edge applications - without over-provisioning flash or sacrificing TrustZone®-based isolation.

Availability

LPC55S06JBD64K is available at Aetrix Electronics and suitable for industrial gateways, secure IoT edge nodes, and automotive body control modules requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for LPC55S06JBD64K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in ARM-based microcontrollers and cryptographic IP.

The LPC55S0x series targets resource-constrained yet security-critical embedded systems, combining TrustZone®, PRINCE, CASPER, and PUF to deliver certified hardware root of trust in a single-chip solution.

FAQ

What is the maximum operating frequency of the LPC55S06JBD64K core?

The LPC55S06JBD64K features an ARM Cortex-M33 core rated for operation up to 96 MHz, driven by the internal Free Running Oscillator (FRO) or PLL-synthesized clocks. This frequency is sustained across the full −40 °C to +105 °C temperature range and 1.8 V to 3.6 V supply voltage, with FRO trimming ensuring ±1% accuracy at 96 MHz over 0 °C to 85 °C and ±2% over the extended range. The LPC55S06JBD64K achieves deterministic real-time performance without external crystal dependency for core timing.

Does the LPC55S06JBD64K support secure boot with public-key cryptography?

Yes, the LPC55S06JBD64K supports secure boot using RSASSA-PKCS1-v1_5 signatures of SHA256 digests, validated against RSA-2048 or RSA-4096 public keys stored in x.509 certificates. It enforces anti-rollback via image key revocation and supports up to four root-of-trust keys in protected flash. The LPC55S06JBD64K implements DICE v2.0 Level 00 for device identity composition and integrates debug authentication to prevent unauthorized firmware access - all verified in the ROM bootloader before application code execution.

How many ADC input channels does the LPC55S06JBD64K provide, and what is its sampling capability?

The LPC55S06JBD64K integrates a 16-bit successive-approximation ADC with nine configurable input channels (supporting up to five differential pairs), capable of simultaneous conversions on two channels within a pair. It achieves a maximum sample rate of 2.0 Msamples/sec with internal or external trigger sources, and includes integrated temperature sensing. The ADC operates independently of CPU load via DMA, and its dedicated VDDA/VREFP supplies ensure <±1 LSB INL across the operating temperature range - critical for precision sensor interfacing in the LPC55S06JBD64K.

What serial communication interfaces are available on the LPC55S06JBD64K?

The LPC55S06JBD64K provides eight Flexcomm interfaces (FC0–FC7), each software-configurable as USART, SPI, I2C, or I2S, plus one dedicated high-speed SPI (FC8). It also includes a CAN FD controller with integrated DMA. Each Flexcomm supports FIFO buffering, fractional baud-rate generation, and timeout detection. The LPC55S06JBD64K's Flexcomm architecture allows dynamic reassignment - for example, FC3 can serve as UART for debugging while FC4 handles I2C sensor polling and FC5 manages SPI flash programming - maximizing peripheral utilization without hardware redesign.

Is the LPC55S06JBD64K pin-compatible with other members of the LPC55S0x family?

Yes, the LPC55S06JBD64K in HTQFP64 packaging shares identical pinout and electrical characteristics with other HTQFP64 variants in the LPC55S0x/LPC550x family, including LPC55S04JBD64 and LPC5506JBD64. All share the same 64-pin mapping, power domains, reset behavior, and peripheral pin assignments - enabling hardware reuse across different flash/SRAM configurations and feature sets. However, functional differences (e.g., CAN FD vs. CAN 2.0, PRINCE presence, PUF availability) require firmware-level validation, as the LPC55S06JBD64K's security features are not mirrored in non-S-series variants.