NXP Semiconductors LPC55S06JBD64Y

Overview

LPC55S06JBD64Y from NXP Semiconductors is a 32-bit ARM Cortex-M33 microcontroller with TrustZone security, PRINCE flash encryption, CASPER crypto co-processor, 256 KB flash, 96 KB SRAM, CAN FD interface, and 45 GPIOs-designed for secure industrial control, IoT edge nodes, and automotive body electronics requiring certified boot and runtime integrity.

For engineers reviewing the LPC55S06JBD64Y datasheet, LPC55S06JBD64Y pinout, LPC55S06JBD64Y application, or LPC55S06JBD64Y equivalent, this page delivers verified specifications, package mapping to HTQFP64, functional pin roles, real-world use cases, and validated alternative parts for secure embedded design.

Technical Context

The LPC55S06JBD64Y implements ARMv8-M architecture with TrustZone-enabled memory isolation, FPU, MPU, and NVIC-enabling secure partitioning of trusted firmware and untrusted applications. Its dual DMA controllers (23+10 channels) offload data movement from the CPU across peripherals including CAN FD, Flexcomm interfaces, and ADC.

CASPER accelerates ECC operations (e.g., ECDSA, ECDH), while PRINCE performs real-time AES-256 encryption/decryption of flash reads/writes. The 16-bit 2.0 Msamples/sec ADC supports simultaneous differential conversions on up to 9 channels, and the SCTimer/PWM provides 10 configurable outputs with state-machine logic.

Key Specifications

Pinout & Package

HTQFP64 package: 64-pin plastic low-profile quad flat package with 0.5 mm pitch, 10 mm × 10 mm body, and exposed thermal pad (connected to VSS). Pin 1 index located at top-left corner per JEDEC MO-220 standard.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar secure microcontroller applications.

Compared with LPC55S16JBD64 and RA6M5GFP64FB, the LPC55S06JBD64Y uniquely combines PRINCE flash encryption, CASPER ECC acceleration, and DICE-compliant Secure Boot in a compact HTQFP64 package-making it the most cost-effective choice for resource-constrained, security-certifiable edge devices.

Availability

LPC55S06JBD64Y is available at Aetrix Electronics and suitable for industrial automation, automotive body electronics, and medical IoT applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for LPC55S06JBD64Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in ARM-based microcontrollers and hardware security IP.

The LPC55S0x series targets secure embedded applications demanding certified boot, runtime integrity, and hardware-accelerated cryptography-specifically designed for industrial control, automotive subsystems, and regulated medical devices.

FAQ

What is the maximum operating frequency of the LPC55S06JBD64Y?

The LPC55S06JBD64Y operates at a maximum CPU frequency of 96 MHz using its ARM Cortex-M33 core. This speed is achievable with the internal 96 MHz Free Running Oscillator (FRO) or PLL-derived clocks. The FRO is factory-trimmed to ±1% accuracy across voltage and 0°C–85°C, ensuring reliable timing without external crystals for many applications. All peripheral clock domains derive from this core clock source.

Does the LPC55S06JBD64Y support secure boot with public-key validation?

Yes, the LPC55S06JBD64Y supports Secure Boot using RSASSA-PKCS1-v1_5 signatures of SHA256 digests, with RSA-2048 and RSA-4096 public key support. It validates images against up to four revocable Root of Trust keys stored in protected flash, and enforces anti-rollback via x.509 certificate serial number revocation. The ROM bootloader handles all verification before executing user code.

How many ADC channels does the LPC55S06JBD64Y support, and what is their resolution?

The LPC55S06JBD64Y integrates a 16-bit successive-approximation ADC with nine input channels (five differential pairs or ten single-ended). It achieves up to 2.0 million samples per second with simultaneous conversion capability on paired differential inputs. Internal reference (VREFP/VSSA) and external reference options are supported, and the ADC connects directly to the integrated temperature sensor.

What package type is used for the LPC55S06JBD64Y, and what are its thermal characteristics?

The LPC55S06JBD64Y uses the HTQFP64 package: a 10 mm × 10 mm, 0.5 mm pitch, low-profile quad flat package with exposed thermal pad. The pad must be soldered to a VSS-connected copper plane for effective heat dissipation. This package supports operation from −40°C to +105°C ambient, and integrates an on-chip DC-DC converter to reduce external power components.

Can the LPC55S06JBD64Y perform hardware-accelerated elliptic curve cryptography?

Yes, the LPC55S06JBD64Y includes the CASPER crypto co-processor, which provides hardware acceleration for Elliptic Curve Cryptography algorithms including ECDSA signature generation/verification and ECDH key agreement. CASPER operates independently of the CPU, reducing latency and power consumption for cryptographic operations compared to software-only implementations.