NXP Semiconductors LPC55S14JBD100Y
- Part No.:
- LPC55S14JBD100Y
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 100-LQFP Exposed Pad
- Datasheet:
-
LPC55S14JBD100Y.pdf
- Description:
- IC MCU 32BIT 128KB FLSH 100HLQFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,000
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Product details
Overview
LPC55S14JBD100 from NXP Semiconductors is a 32-bit Arm Cortex-M33 microcontroller with TrustZone security, PRINCE flash encryption, CASPER crypto acceleration, 128 KB on-chip flash, 80 KB SRAM, and dual USB (full-speed + high-speed) supporting crystal-less operation. It integrates CAN FD, a 16-bit 2.0 Msamples/sec ADC with simultaneous differential conversion, SCTimer/PWM, PLU, temperature sensor, and operates across −40 °C to +105 °C for industrial edge-node control.
For engineers reviewing the LPC55S14JBD100 datasheet, LPC55S14JBD100 pinout, LPC55S14JBD100 application, or LPC55S14JBD100 equivalent, key selection criteria include secure boot support (RSA-2048/4096), PUF-based key generation, PRINCE real-time flash encryption, Flexcomm configurable serial interfaces (up to nine USART/SPI/I2C/I2S), and HLQFP100 package compatibility with 64 GPIOs.
Technical Context
The LPC55S14JBD100 implements Arm TrustZone® at the hardware level to isolate secure and non-secure execution environments, enabling secure firmware updates and cryptographic key protection via integrated PUF and AES-256. Its CASPER co-processor accelerates ECC operations, while PRINCE performs real-time on-the-fly encryption/decryption of flash contents without software overhead.
It features two DMA controllers (23-channel DMA0 and 10-channel DMA1), five 32-bit general-purpose timers, one SCTimer/PWM with 16 capture/match registers and flexible peripheral routing, and nine Flexcomm interfaces-each software-configurable as USART, SPI, I2C, or I2S-with dedicated FIFOs and fractional baud-rate generators.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 @ up to 150 MHz with FPU, MPU, and TrustZone® for hardware-enforced secure/non-secure partitioning. |
| Memory | 128 KB flash (512-byte page erase/write) + 80 KB SRAM (16 KB code bus, 64 KB system bus including 16 KB USB SRAM). |
| Security | PRINCE flash encryption/decryption, CASPER ECC accelerator, PUF-generated keys (64–4096 bits), SHA2/AES-256, TRNG, secure boot with RSA-2048/4096 and x.509 certificate validation. |
| Analog | 16-bit ADC with 2.0 Msamples/sec sampling rate, simultaneous dual-channel differential conversion, integrated temperature sensor and comparator. |
| Connectivity | CAN FD controller with dedicated DMA, USB 2.0 full-speed + high-speed host/device with on-chip PHY and crystal-less FS mode, nine Flexcomm interfaces (configurable as USART/SPI/I2C/I2S). |
| Package | HLQFP100: 100-pin plastic low-profile quad flat package, 14 × 14 × 0.5 mm body, 0.5 mm pitch, 64 GPIOs available. |
| Operating Range | Single 1.8 V–3.6 V supply; industrial temperature range −40 °C to +105 °C with integrated DC-DC converter and PMU power management. |
Pinout & Package
HLQFP100 package: 100-lead plastic low-profile quad flat package, 14 mm × 14 mm body, 0.5 mm pitch, exposed thermal pad, RoHS-compliant. Pin 1 index located at top-left corner with notch or dot marking.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDA | Analog power supply | 1.8 V–3.6 V analog domain supply; requires local decoupling for ADC/comparator stability. |
| VSSA | Analog ground | Dedicated analog reference return; must be separated from digital ground at single-point connection. |
| PIO0_0/ACMP0_A | GPIO / comparator input A | Configurable digital I/O or analog comparator input when ANAMODE=1; supports secure GPIO function. |
| PIO0_9/ACMP0_B | GPIO / comparator input B | Paired with PIO0_0 for differential comparator operation; enables zero-crossing detection in sensor interfaces. |
| ADC0_1 | ADC channel 1 input | Single-ended or differential positive input (with ADC0_11); supports 16-bit precision at 2.0 Msamples/sec with internal trigger options. |
| USB0_DP / USB0_DM | USB full-speed differential pair | On-chip PHY supports crystal-less operation in device mode; requires 27 Ω series termination per line. |
| USB1_DP / USB1_DM | USB high-speed differential pair | High-speed PHY with integrated termination; supports host/device roles and link training per USB 2.0 HS specification. |
| CAN0_TD / CAN0_RD | CAN FD transmit/receive | Direct interface to external CAN transceiver; supports bit rates up to 5 Mbit/s with flexible data phase timing. |
| XTAL_IN / XTAL_OUT | 32.768 kHz crystal oscillator | Drives RTC and WWDT; internal load capacitors programmable via API to eliminate external components. |
| SWD_CLK / SWD_IO | Serial Wire Debug interface | Two-pin debug port supporting breakpoints, watchpoints, and Serial Wire Output trace; enabled by default at reset. |
Key Features
| Feature | Design Value |
|---|---|
| TrustZone® isolation | Hardware-enforced separation of secure/non-secure memory and peripherals, enabling certified secure boot and runtime attestation. |
| PRINCE flash encryption | Real-time AES-128 encryption/decryption of flash reads/writes without CPU intervention or performance penalty. |
| CASPER crypto engine | Hardware acceleration for ECC scalar multiplication (NIST P-256/P-384), reducing signature generation time by >10× vs. software-only implementation. |
| Flexcomm serial interfaces | Nine software-configurable peripherals supporting UART, SPI, I2C, and I2S - each with independent clocking, FIFO, and DMA-ready signaling. |
| SCTimer/PWM | State-configurable timer with 16 match/capture registers, event-driven state transitions, and direct peripheral-to-peripheral routing for motor control timing chains. |
| PUF key generation | SRAM-based physical unclonable function producing device-unique 256-bit root keys; eliminates need for external secure element or key provisioning infrastructure. |
Applications
| Industrial PLC Edge Node | Secure IoT Gateway |
|---|---|
Use Scenario: Real-time monitoring and control of field devices (valves, sensors, actuators) in hazardous or remote locations with over-the-air firmware updates. IC Role / Device Role / Timing Role: Main application processor executing deterministic control loops, managing CAN FD fieldbus communication, and enforcing secure boot before loading updated logic. Use Value: PRINCE encryption protects firmware integrity during wireless updates; SCTimer/PWM delivers precise PWM outputs for servo drive control; −40 °C to +105 °C rating ensures reliability in uncontrolled enclosures. | Use Scenario: Aggregating and preprocessing sensor data from multiple protocols (Modbus RTU, BLE, LoRaWAN) before forwarding to cloud infrastructure. IC Role / Device Role / Timing Role: Secure protocol bridge with TLS offload via CASPER and SHA2, USB host for peripheral attachment, and Flexcomm interfaces for legacy serial connectivity. Use Value: PUF-derived keys enable unique device identity and mutual authentication; dual USB (FS+HS) supports both configuration dongles and high-bandwidth data export; 80 KB SRAM accommodates multiple concurrent protocol stacks. |
| Medical Diagnostic Sensor Hub | Automotive Body Control Module |
Use Scenario: Signal conditioning and real-time analysis of ECG, temperature, and motion data in portable diagnostic equipment requiring regulatory compliance (IEC 62304). IC Role / Device Role / Timing Role: Safety-critical data acquisition controller with ADC oversampling, comparator-based alarm triggering, and secure storage of calibration parameters. Use Value: 16-bit 2.0 Msamples/sec ADC enables high-fidelity waveform capture; Code Watchdog detects unexpected program flow deviations; secure GPIO prevents unauthorized peripheral access. | Use Scenario: Centralized control of lighting, door locks, window lifts, and HVAC in entry-level vehicles using CAN FD backbone. IC Role / Device Role / Timing Role: CAN FD node with message filtering, DMA-accelerated frame handling, and secure firmware update capability for ECU reprogramming. Use Value: CAN FD module supports >2x payload throughput vs. CAN 2.0; secure boot with revocable RoT keys enables safe OTA updates; 64 GPIOs simplify discrete load driving without external expanders. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Arm Cortex-M33 microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC55S16JBD100 | 256 KB flash, 96 KB SRAM, identical security/peripheral set; higher memory capacity but same package and pinout. | Preferred where larger firmware images or dual-bank secure updates require extra flash space. | Select LPC55S16JBD100 when application firmware exceeds 128 KB or requires redundant image storage. |
| LPC55S06JBD100 | 64 KB flash, 48 KB SRAM, no PUF or CASPER; retains TrustZone, PRINCE, USB FS/HS, CAN FD, and Flexcomm interfaces. | Suitable for cost-sensitive, lower-complexity designs where cryptographic acceleration and large memory are unnecessary. | Choose LPC55S06JBD100 for basic secure control tasks without ECC or large OTA payloads. |
Compared with LPC55S14JBD100, LPC55S16JBD100 offers scalable memory headroom within identical footprint and security architecture, while LPC55S06JBD100 reduces cost and complexity by removing PUF/CASPER - making it viable for non-cryptographic secure boot use cases.
Availability
LPC55S14JBD100 is available at Aetrix Electronics and suitable for industrial automation, secure IoT gateways, medical sensor hubs, and automotive body control modules requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for LPC55S14JBD100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in Arm-based microcontrollers and trusted execution environments.
The LPC55S1x series targets resource-constrained, security-critical embedded systems requiring hardware-rooted trust, real-time performance, and multi-protocol connectivity - especially where regulatory compliance and firmware integrity are mandatory.
FAQ
What is the maximum operating frequency of the LPC55S14JBD100?
The LPC55S14JBD100 features an Arm Cortex-M33 core rated for operation up to 150 MHz. This maximum frequency is achievable under specified voltage (1.8–3.6 V) and temperature (−40 °C to +105 °C) conditions with appropriate clock source configuration - typically using PLL0 driven by the internal 96 MHz FRO or external crystal. The core includes a floating-point unit and memory protection unit to sustain deterministic real-time performance at this speed.
Does the LPC55S14JBD100 support secure boot with public-key cryptography?
Yes, the LPC55S14JBD100 supports secure boot using RSASSA-PKCS1-v1_5 signatures over SHA256 digests, with verification against RSA-2048 or RSA-4096 public keys stored in x.509 certificates. Up to four root-of-trust keys can be provisioned in protected flash, and anti-rollback is enforced via image key revocation using the certificate serial number field - all implemented in ROM bootloader without software dependency.
How many Flexcomm interfaces does the LPC55S14JBD100 provide, and what protocols do they support?
The LPC55S14JBD100 provides nine Flexcomm interfaces (Flexcomm 0–8), each configurable in software as USART, SPI, I2C, or I2S. Flexcomm 8 is dedicated to high-speed SPI only. All Flexcomm modules include FIFOs, independent clocking (including fractional baud-rate generators), and DMA-ready signaling - enabling concurrent multi-protocol communication such as USB-to-Modbus bridging or audio streaming with sensor telemetry.
What analog capabilities are integrated into the LPC55S14JBD100?
The LPC55S14JBD100 integrates a 16-bit ADC with 2.0 Msamples/sec maximum sample rate, supporting simultaneous conversions on differential channel pairs. It also includes an analog comparator with five inputs and selectable internal/external references, an integrated temperature sensor connected to the ADC, and dedicated analog power (VDDA/VSSA) domains with separate decoupling requirements to ensure signal integrity.
Is the LPC55S14JBD100 pin-compatible with other members of the LPC55S1x family?
Yes, the LPC55S14JBD100 in HLQFP100 package is pin-compatible with LPC55S16JBD100, LPC5514JBD100, and LPC5516JBD100 - all sharing identical 100-pin layout, signal mapping, and power/ground pin assignments. This allows direct substitution in existing PCB designs when upgrading flash/SRAM capacity or adjusting security feature sets, provided firmware is reconfigured to match the target variant's memory map and peripheral enablement.
LPC55S14JBD100Y Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 100-LQFP Exposed Pad
- Series:
- LPC55S1x
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit Single-Core
- Speed:
- 150MHz
- Connectivity:
- CAN FD, Flexcomm, I2C, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, PWM, RNG, WDT
- Number of I/O:
- 64
- Program Memory Size:
- 128KB (128K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 80K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 10x16b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC55S14JBD100Y FAQ
1.How can I place an order for LPC55S14JBD100Y through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC55S14JBD100Y on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC55S14JBD100Y reliable?
The price and inventory of LPC55S14JBD100Y are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC55S14JBD100Y is usually 5 days.
3.What payment methods are accepted for LPC55S14JBD100Y?
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LPC55S14JBD100Y orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC55S14JBD100Y order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC55S14JBD100Y?
For technical support, including LPC55S14JBD100Y datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC55S14JBD100Y requirements.
6.How does Aetrix verify that LPC55S14JBD100Y is sourced from the original manufacturer or authorized distributors?
All LPC55S14JBD100Y products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC55S14JBD100Y meets industry standards.
7.What is the process for return or replacement of LPC55S14JBD100Y?
All LPC55S14JBD100Y units undergo pre-shipment inspection (PSI). If there is an issue with LPC55S14JBD100Y, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC55S14JBD100Y part is unused and in its original packaging.
Return procedure for LPC55S14JBD100Y:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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