NXP Semiconductors LPC55S16JBD100E

Overview

LPC55S16JBD100E from NXP Semiconductors is a 32-bit Arm Cortex-M33 microcontroller with TrustZone security, PRINCE flash encryption, CASPER crypto acceleration, 256 KB on-chip flash, 96 KB SRAM, and dual USB (FS + HS) support. It integrates CAN FD, a 16-bit 2.0 Msamples/sec ADC, SCTimer/PWM, PLU, temperature sensor, and secure boot for industrial edge nodes requiring robust firmware integrity and real-time control.

For engineers reviewing the LPC55S16JBD100E datasheet, LPC55S16JBD100E pinout, LPC55S16JBD100E application, or LPC55S16JBD100E equivalent, this page delivers verified specifications, package mapping to HLQFP100, functional pin roles, security architecture details, and validated alternative parts for secure embedded design evaluation.

Technical Context

The LPC55S16JBD100E implements Arm TrustZone to isolate secure and non-secure execution environments, with hardware-enforced memory protection via MPU and secure debug authentication using RSA-2048/4096. Its CASPER co-processor accelerates ECC operations, while PRINCE enables real-time AES-256 encryption/decryption of flash contents during read/write.

It features two DMA controllers (23+10 channels), nine Flexcomm interfaces configurable as USART/SPI/I²C/I²S, dual USB PHYs (full-speed crystal-less and high-speed), and a programmable logic unit (PLU) for glue logic offload. The 150 MHz Cortex-M33 core includes FPU, DSP instructions, and NVIC with NMI support.

Key Specifications

Pinout & Package

HLQFP100 package with 100 leads, body size 14 mm × 14 mm × 0.5 mm, 0.5 mm pitch, exposed thermal pad, RoHS-compliant. Pinout supports JTAG boundary scan, SWD debug (PIO0_11/PIO0_12), USB FS/HS PHY routing, CAN FD transceiver interface, and dual crystal oscillator inputs (12–32 MHz and 32.768 kHz).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Arm Cortex-M33 microcontroller applications.

Compared with LPC55S16JBD100E, LPC55S06JBD100 offers cost reduction without sacrificing package compatibility or core security features, while RA6M5GFP100AA00 trades NXP's hardware-accelerated security for greater raw compute and memory-requiring architectural trade-offs in secure boot and runtime encryption design.

Availability

LPC55S16JBD100E is available at Aetrix Electronics and suitable for industrial automation, automotive gateway systems, and medical IoT devices requiring stable component supply, long-term lifecycle support, and certified secure silicon.

Supply support for LPC55S16JBD100E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in Arm-based microcontrollers and trusted execution environments.

The LPC55S1x series is designed for resource-constrained, security-critical embedded applications demanding hardware-enforced isolation, real-time performance, and seamless integration of cryptography, analog sensing, and multi-protocol connectivity.

FAQ

What is the maximum operating frequency of the LPC55S16JBD100E?

The LPC55S16JBD100E operates at up to 150 MHz using its Arm Cortex-M33 core. This frequency is achievable with PLL0 or PLL1 driven by internal FRO (12 MHz), external crystal (12–32 MHz), or RTC oscillator (32.768 kHz). The FRO is factory-trimmed to ±1% accuracy over 0 °C to 85 °C for date codes 2044 and later, ensuring stable clocking without external components in many designs. LPC55S16JBD100E maintains full peripheral functionality-including USB HS, CAN FD, and ADC sampling-at this maximum rate.

Does the LPC55S16JBD100E support crystal-less USB full-speed operation?

Yes, the LPC55S16JBD100E supports crystal-less USB full-speed device operation using its internal 48 MHz clock derived from the FRO. This eliminates the need for an external 48 MHz crystal or oscillator, reducing BOM cost and PCB area. The feature is implemented in hardware and enabled via ROM bootloader configuration; application firmware must initialize the USB controller with the appropriate clock source. LPC55S16JBD100E does not support crystal-less high-speed USB-HS operation requires the external 12 MHz crystal.

How does the PRINCE module function in the LPC55S16JBD100E?

The PRINCE module in the LPC55S16JBD100E performs real-time AES-256 encryption and decryption of on-chip flash memory. During write operations, plaintext data is encrypted before storage; during read operations, ciphertext is decrypted on-the-fly before being delivered to the core. This occurs transparently in hardware with no software intervention or performance penalty. PRINCE supports multiple encrypted regions, enabling secure firmware updates and asset protection. LPC55S16JBD100E uses PRINCE in conjunction with secure boot to ensure only authenticated, encrypted images execute.

What debug interfaces are available on the LPC55S16JBD100E?

The LPC55S16JBD100E provides Serial Wire Debug (SWD) via PIO0_11 (SWDIO) and PIO0_12 (SWCLK), supporting eight breakpoints and four watchpoints. It also includes Serial Wire Output (SWO) on PIO0_8 for real-time trace streaming. JTAG boundary scan is supported on PIO0_2–PIO0_6 but is disabled during normal debug operation. Debug authentication uses RSA-2048/4096 to prevent unauthorized access. LPC55S16JBD100E does not support SWD with JTAG combined mode-SWD is the primary debug interface for development and production programming.

Can the LPC55S16JBD100E operate in deep power-down mode with RTC wake-up?

Yes, the LPC55S16JBD100E supports deep power-down mode with RAM retention and RTC wake-up capability. The RTC runs in the always-on power domain using either the 32 kHz FRO or an external 32.768 kHz crystal, providing 1 s resolution and wake-up from all low-power states-including deep power-down-with 1 ms resolution. Wake-up events can be configured via alarm or periodic interrupt. LPC55S16JBD100E retains 96 KB SRAM content during deep power-down, enabling fast resume with full context preservation, critical for battery-powered edge sensors.