NXP Semiconductors LPC55S16JEV59E
- Part No.:
- LPC55S16JEV59E
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 59-VFBGA
- Datasheet:
-
LPC55S16JEV59E.pdf
- Description:
- IC MCU 32BIT 256KB FLASH 59BGA
- Quantity:
- Payment:

- Shipping:

Inventory:490
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Product details
Overview
LPC55S16JEV59E from NXP Semiconductors is an Arm Cortex-M33-based microcontroller with TrustZone security, 256 KB flash, 96 KB SRAM, PRINCE real-time flash encryption, CASPER crypto co-processor, and CAN FD interface - deployed in secure industrial gateways requiring firmware integrity, encrypted OTA updates, and deterministic fieldbus communication.
For engineers reviewing the LPC55S16JEV59E datasheet, LPC55S16JEV59E pinout, LPC55S16JEV59E application, or LPC55S16JEV59E equivalent, key selection criteria include VFBGA59 package footprint, 37 GPIO count, high-speed USB (HS) support without full-speed PHY, and verified TrustZone + PUF + Secure Boot implementation for certified IoT edge nodes.
Technical Context
The LPC55S16JEV59E implements Arm TrustZone to isolate secure and non-secure execution environments, with hardware-enforced memory protection via MPU and secure boot using RSA-2048/4096 signatures validated against up to four revocable Root of Trust keys stored in protected flash. Its CASPER co-processor accelerates ECC operations, while PRINCE enables transparent AES-128 encryption/decryption of on-chip flash during read/write cycles.
It integrates dual DMA controllers (23+10 channels), nine Flexcomm interfaces configurable as USART/SPI/I2C/I2S, a 16-bit 2.0 Msamples/sec ADC with simultaneous differential conversion, and SCTimer/PWM with 16 capture/match registers - all accessible within the TrustZone-secured peripheral matrix and clocked by PLL0/PLL1 derived from FRO, crystal, or RTC sources.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 @ 150 MHz with FPU, MPU, and TrustZone isolation |
| Memory | 256 KB on-chip flash with PRINCE encryption; 96 KB SRAM (16 KB code + 64 KB system + 16 KB USB) |
| Security | Secure Boot (RSA-2048/4096), PUF-generated keys, SHA2/AES-256, CASPER ECC acceleration, Code Watchdog |
| Connectivity | CAN FD controller with dedicated DMA; USB 2.0 high-speed host/device (no full-speed PHY); 9 Flexcomm interfaces |
| Analog | 16-bit ADC @ 2.0 Msamples/sec with 5 differential/10 single-ended channels and integrated temperature sensor |
| Timers | 5× 32-bit general-purpose timers, SCTimer/PWM (16 capture/match), RTC with wake-up from deep power-down |
| Package | VFBGA59 (4 mm × 4 mm, 0.4 mm pitch, 37 GPIO) |
| Operating Range | −40 °C to +105 °C, single 1.8–3.6 V supply with internal DC-DC converter |
Pinout & Package
VFBGA59 package: 4 mm × 4 mm body, 0.4 mm ball pitch, 59-ball array with 37 user-accessible GPIOs. Ball layout optimized for signal integrity in space-constrained industrial control modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PIO0_0 / ACMP0_A | Analog comparator input A or GPIO | Enables analog threshold detection when ANAMODE=1; default reset state is high-impedance digital I/O |
| PIO0_5 / TDI | JTAG test data input or CAN0_TD | Boot source selection pin at reset; drives CAN0 transmitter output when configured for CAN FD |
| PIO0_10 / ADC0_1 | ADC channel 1A input or GPIO | Supports differential pair with PIO0_11 for noise-immune current sensing in motor control |
| PIO0_12 / SWDIO | Serial Wire Debug I/O | Primary debug interface; enabled by default at reset with internal pull-down for reliable connection |
| USB_DP / USB_DM | USB 2.0 HS differential pair | Direct connection to USB HS PHY; no external crystal required for device mode operation |
Key Features
| Feature | Design Value |
|---|---|
| PRINCE Flash Encryption | Hardware-accelerated AES-128 on-the-fly encryption/decryption enabling secure firmware updates without software overhead |
| CASPER Crypto Engine | Dedicated hardware for ECC scalar multiplication, reducing Elliptic Curve signature generation time by >10× vs. software-only execution |
| Flexcomm Interface Flexibility | Nine independent serial peripherals each configurable as USART/SPI/I2C/I2S - eliminates need for external protocol translators in multi-interface systems |
| SCTimer/PWM Precision | 16 capture/match registers with event/state machine logic enable complex PWM waveforms for BLDC motor commutation or lighting control |
| PUF-Based Key Generation | SRAM-based Physical Unclonable Function produces device-unique 64–4096 bit keys, eliminating external secure element dependency |
| Micro-Tick Timer Wake-Up | 42-bit free-running OS timer clocked at 32 kHz provides >4-year continuous timing and wake-up from deep-sleep with ±1% accuracy |
Applications
| Industrial PLC Edge Node | Secure Smart Meter |
|---|---|
Use Scenario: Field-deployed programmable logic controller collecting sensor data over CAN FD and forwarding encrypted telemetry via cellular modem. IC Role / Device Role / Timing Role: Main application processor executing real-time control tasks, managing CAN FD frame scheduling, and performing AES-256 encryption of metering logs before transmission. Use Value: PRINCE-encrypted flash prevents firmware tampering; TrustZone isolates metering algorithms from communication stack; 37 GPIO support discrete I/O expansion without external port expanders. |
Use Scenario: Revenue-grade electricity meter requiring cryptographic authentication of firmware updates and tamper-evident logging of voltage/current anomalies. IC Role / Device Role / Timing Role: Trusted execution environment host running DICE-compliant secure boot, PUF-derived key storage, and SHA256 hash verification of SB2 update packages. Use Value: RSA-4096 root key revocation prevents compromised update servers; integrated 16-bit ADC achieves <±0.1% THD for Class 0.2 metering compliance; RTC alarm triggers secure log dumps on power loss. |
| Medical Diagnostic Sensor Hub | Automotive Body Control Module |
Use Scenario: Portable ultrasound probe hub aggregating analog front-end data from multiple transducer arrays and streaming compressed frames via USB HS to tablet host. IC Role / Device Role / Timing Role: High-bandwidth data concentrator using DMA-driven ADC sampling, SCTimer-synchronized pulse generation, and USB HS bulk transfers with zero-copy buffering. Use Value: 2.0 Msamples/sec ADC supports 12-bit resolution at 160 kHz per channel; USB HS PHY enables >30 MB/s sustained throughput; 105°C rating permits under-hood deployment near thermal sensors. |
Use Scenario: Zone controller managing door locks, lighting, and HVAC actuators via CAN FD, with secure OTA updates and intrusion detection via analog sensor fusion. IC Role / Device Role / Timing Role: Safety-aware MCU executing ASIL-B compliant diagnostics, monitoring comparator inputs for forced entry, and validating CAN FD message authenticity using embedded HASH-AES engine. Use Value: Code Watchdog detects runtime instruction flow corruption; secure GPIO prevents unauthorized pin reconfiguration; 32-bit MRT timers provide precise PWM dimming for LED lighting without CPU load. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar secure microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC55S16JBD64 | HTQFP64 package (64-pin), 36 GPIO, includes USB full-speed PHY alongside HS | Preferred where board layout requires through-hole mounting or additional GPIO for legacy UART/LED interfaces | Select when USB FS compatibility is mandatory and PCB area allows larger footprint |
| LPC55S14JEV59 | Same VFBGA59 package but reduced memory: 128 KB flash, 80 KB SRAM, identical security/peripheral set | Cost-optimized variant for firmware with smaller code size and lower RAM footprint | Choose for volume-sensitive designs where 256 KB flash headroom is unnecessary |
Compared with LPC55S16JEV59E, the LPC55S16JBD64 adds USB full-speed capability at the cost of larger package and higher BOM cost, while the LPC55S14JEV59 retains identical security and peripheral features but trades flash/SRAM capacity for lower unit price - making LPC55S16JEV59E optimal for space-constrained, high-security applications demanding maximum on-chip memory.
Availability
LPC55S16JEV59E is available at Aetrix Electronics and suitable for industrial automation, smart energy metering, and medical sensor hub applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing from authorized NXP channels.
Supply support for LPC55S16JEV59E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with core expertise in Arm-based MCUs and embedded security IP.
The LPC55S1x series is designed for resource-constrained edge devices requiring certified security, real-time performance, and mixed-signal integration - targeting applications where firmware integrity, encrypted data handling, and low-power operation are non-negotiable.
FAQ
What security features are implemented in the LPC55S16JEV59E?
The LPC55S16JEV59E integrates Arm TrustZone for hardware-enforced memory isolation, PRINCE for real-time AES-128 flash encryption, CASPER for ECC acceleration, PUF-based key generation, SHA2/AES-256 engines, RSA-2048/4096 secure boot, and Code Watchdog for runtime integrity checking - all verified in the NXP LPC55S16JEV59E datasheet Rev. 1.8.
Does the LPC55S16JEV59E support USB full-speed operation?
No, the LPC55S16JEV59E supports only USB 2.0 high-speed (HS) host/device operation with integrated HS PHY. It does not include a full-speed (FS) PHY - unlike variants such as LPC55S16JBD64. USB FS functionality is absent in the LPC55S16JEV59E silicon design per Table 2 of the datasheet.
What is the GPIO count and package type of the LPC55S16JEV59E?
The LPC55S16JEV59E uses a VFBGA59 package (4 mm × 4 mm, 0.4 mm pitch) with 37 user-configurable GPIO pins. This is confirmed in Table 1 and Table 2 of the NXP LPC55S1x/LPC551x datasheet Rev. 1.8, distinguishing it from 64- or 100-pin variants.
Can the LPC55S16JEV59E execute secure boot with external flash?
The LPC55S16JEV59E supports secure boot only from on-chip flash or PRINCE-encrypted regions thereof. It does not authenticate or execute images directly from external SPI flash - boot sources are limited to internal flash, ROM bootloader, or ISP interfaces per Section 2.2 of the datasheet. External flash must be managed via application-level drivers after secure boot completes.
What ADC performance does the LPC55S16JEV59E deliver?
The LPC55S16JEV59E features a 16-bit SAR ADC capable of 2.0 million samples per second, supporting simultaneous conversions on differential channel pairs. It includes five differential inputs (10 single-ended), internal temperature sensor, and programmable gain - meeting requirements for precision current/voltage monitoring in the LPC55S16JEV59E's target industrial applications.
LPC55S16JEV59E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 59-VFBGA
- Series:
- LPC55S1x
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit Single-Core
- Speed:
- 150MHz
- Connectivity:
- CAN FD, Flexcomm, I2C, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, PWM, RNG, WDT
- Number of I/O:
- 37
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 96K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 10x16b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC55S16JEV59E FAQ
1.How can I place an order for LPC55S16JEV59E through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC55S16JEV59E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC55S16JEV59E reliable?
The price and inventory of LPC55S16JEV59E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC55S16JEV59E is usually 5 days.
3.What payment methods are accepted for LPC55S16JEV59E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC55S16JEV59E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC55S16JEV59E?
LPC55S16JEV59E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC55S16JEV59E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC55S16JEV59E?
For technical support, including LPC55S16JEV59E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC55S16JEV59E requirements.
6.How does Aetrix verify that LPC55S16JEV59E is sourced from the original manufacturer or authorized distributors?
All LPC55S16JEV59E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC55S16JEV59E meets industry standards.
7.What is the process for return or replacement of LPC55S16JEV59E?
All LPC55S16JEV59E units undergo pre-shipment inspection (PSI). If there is an issue with LPC55S16JEV59E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC55S16JEV59E part is unused and in its original packaging.
Return procedure for LPC55S16JEV59E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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