NXP Semiconductors LPC55S16JEV98K
- Part No.:
- LPC55S16JEV98K
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 98-VFBGA
- Datasheet:
-
LPC55S16JEV98K.pdf
- Description:
- IC MCU 32BIT 256KB FLASH 98VFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:1,300
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Product details
Overview
LPC55S16JEV98K from NXP Semiconductors is a 32-bit Arm Cortex-M33 microcontroller with TrustZone security, PRINCE flash encryption, CASPER crypto acceleration, 256 KB on-chip flash, 96 KB SRAM, and dual USB (FS + HS) plus CAN FD interfaces - deployed in industrial control, secure IoT edge nodes, and automotive body electronics requiring certified boot and runtime integrity.
For engineers reviewing the LPC55S16JEV98K datasheet, LPC55S16JEV98K pinout, LPC55S16JEV98K application, or LPC55S16JEV98K equivalent, key selection criteria include TrustZone-enforced memory isolation, PRINCE-encrypted flash update capability, CASPER-accelerated ECC operations, and VFBGA98 package compatibility with high-density PCB layouts.
Technical Context
The LPC55S16JEV98K implements Arm v8-M architecture with TrustZone, enabling hardware-isolated secure and non-secure execution environments. Its CASPER co-processor offloads elliptic curve cryptography (ECC), while PRINCE performs real-time AES-128 encryption/decryption of flash reads and writes.
It integrates two DMA controllers (23+10 channels), nine Flexcomm peripherals configurable as USART/SPI/I²C/I²S, SCTimer/PWM with 16 capture/match registers, and a 16-bit 2.0 Msamples/sec ADC supporting simultaneous differential conversions - all synchronized under a unified clocking system with FRO, PLLs, and crystal oscillators.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 @ up to 150 MHz with FPU, MPU, and TrustZone for secure partitioning |
| Memory | 256 KB on-chip flash (512-byte page erase) + 96 KB SRAM (16 KB code bus + 64 KB system bus + 16 KB USB SRAM) |
| Security | PRINCE flash encryption, CASPER ECC acceleration, PUF-based key generation, SHA2/AES/TRNG, secure boot with RSA-2048/4096 |
| Analog | 16-bit ADC @ 2.0 Msamples/sec with 5 differential/10 single-ended channels and integrated temperature sensor |
| Connectivity | CAN FD, USB 2.0 full-speed + high-speed (on-chip PHY), nine Flexcomm interfaces (USART/SPI/I²C/I²S), I²C Fast-mode Plus (1 Mbit/s) |
| Timers | Five 32-bit general-purpose timers, SCTimer/PWM (8 inputs/10 outputs), RTC with wake-up from deep power-down, WWDT |
| Package | VFBGA98 (7 × 7 × 0.5 mm, 0.4 mm ball pitch) per SOT1982-1 |
Pinout & Package
VFBGA98 package (SOT1982-1): 98-ball thin fine-pitch BGA, 7 mm × 7 mm body, 0.4 mm ball pitch, exposed thermal pad, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PIO0_0 / ACMP0_A | Analog comparator input A / GPIO | Configurable as digital I/O or analog comparator input when ANAMODE=1; supports secure GPIO mode |
| PIO0_5 / TDI | JTAG test data input / boot select | State at reset determines boot source (flash, USB, UART); enables boundary scan and ISP programming |
| PIO0_11 / SWDIO | Serial Wire Debug I/O | Dedicated debug interface pin; active during reset to support early firmware validation |
| PIO0_12 / SWCLK | Serial Wire Debug clock | Provides clock for SWD protocol; required for secure debug authentication handshake |
| USB_DP / USB_DM | USB 2.0 HS/FS differential pair | On-chip PHY supports crystal-less FS operation and HS signaling; routed to dedicated USB pads |
| CAN0_TD / CAN0_RD | CAN FD transmit/receive | Dedicated CAN FD transceiver pins with internal termination; support bit rates up to 5 Mbit/s |
Key Features
| Feature | Design Value |
|---|---|
| TrustZone-enabled memory isolation | Hardware-enforced separation between secure firmware (bootloader, crypto keys) and non-secure application code |
| PRINCE real-time flash encryption | Transparent AES-128 encryption/decryption during flash read/write - no software overhead or latency penalty |
| CASPER cryptographic co-processor | Hardware acceleration for ECC scalar multiplication (NIST P-256/P-384), reducing signature verification time by >10× vs. software |
| Flexcomm serial peripheral flexibility | Nine independent interfaces, each software-configurable as USART/SPI/I²C/I²S - eliminates need for external bridge ICs |
| Secure boot with anti-rollback | RSASSA-PKCS1-v1_5 signature verification using SHA256 digest and revocable root-of-trust keys stored in protected flash |
Applications
| Industrial PLC Controller | Secure Smart Meter |
|---|---|
Use Scenario: Real-time deterministic control of motor drives and I/O modules in factory automation systems with remote firmware updates. IC Role / Device Role / Timing Role: Main application processor executing control algorithms, managing CAN FD fieldbus communication, and enforcing secure OTA update policy via PRINCE and secure boot. Use Value: TrustZone isolates safety-critical control logic from network-facing firmware update handlers; CASPER accelerates DICE-compliant device identity provisioning. |
Use Scenario: Tamper-resistant electricity meter with encrypted consumption logging, remote tariff updates, and physical attack detection. IC Role / Device Role / Timing Role: Secure system-on-chip handling metrology ADC sampling, AES-encrypted data storage, and TLS handshake offload via CASPER. Use Value: PUF-generated keys prevent cloning; PRINCE ensures flash contents remain confidential even if memory is extracted; RTC enables time-stamped audit logs. |
| Automotive Body Control Module | Medical Edge Sensor Hub |
Use Scenario: Centralized lighting, door lock, and climate control unit requiring ASIL-B compliance and secure diagnostic access. IC Role / Device Role / Timing Role: Safety-aware MCU running AUTOSAR OS, managing LIN/CAN FD gateways, and authenticating service tools via Debug Authentication Protocol v1.1. Use Value: Code Watchdog validates instruction flow integrity; WWDT prevents infinite loops in safety monitors; secure GPIO blocks unauthorized pin reconfiguration. |
Use Scenario: Wireless patient monitoring node aggregating ECG, SpO₂, and temperature data with HIPAA-compliant local encryption before BLE transmission. IC Role / Device Role / Timing Role: Low-power sensor fusion hub performing ADC oversampling, noise filtering, and AES-256 payload encryption prior to wireless handoff. Use Value: 2.0 Msamples/sec ADC captures high-fidelity biosignals; TRNG feeds cryptographically secure session keys; deep-sleep modes extend battery life beyond 12 months. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar secure microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC55S06JEV98 | 128 KB flash, 80 KB SRAM, no PRINCE module, same CASPER/TrustZone/USB/ADC specs | Suitable for cost-sensitive designs where encrypted firmware updates are not required | Select when flash size and PRINCE are non-critical; retains identical VFBGA98 footprint and peripheral set |
| RA6M5GFPJAA0 | Arm Cortex-M33 @ 200 MHz, 1 MB flash, 384 KB SRAM, no CASPER, Renesas Secure Crypto Engine instead of PRINCE | Targets higher-performance HMI and gateway applications with larger code base and different crypto acceleration model | Choose for extended memory headroom and Renesas ecosystem integration; requires layout change due to LQFP144 package |
Compared with LPC55S16JEV98K, LPC55S06JEV98 reduces flash and removes PRINCE but maintains pin compatibility and security features, while RA6M5GFPJAA0 offers greater memory and speed at the cost of package change and divergent crypto architecture.
Availability
LPC55S16JEV98K is available at Aetrix Electronics and suitable for industrial control systems, secure IoT gateways, and automotive body electronics requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for LPC55S16JEV98K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with headquarters in Eindhoven, Netherlands.
The LPC55S1x series is designed for embedded applications demanding robust security, real-time performance, and low-power operation - targeting secure edge devices where TrustZone, PRINCE, and CASPER collectively enforce hardware-rooted trust.
FAQ
What security features does the LPC55S16JEV98K provide for secure boot?
The LPC55S16JEV98K implements secure boot using RSASSA-PKCS1-v1_5 signatures over SHA256 digests, supports RSA-2048/4096 public keys, stores up to four revocable Root of Trust keys in protected flash, and enforces anti-rollback via image key certificate revocation. The LPC55S16JEV98K also integrates NXP Debug Authentication Protocol v1.0/v1.1 to authenticate debug sessions before granting access.
Does the LPC55S16JEV98K support crystal-less USB full-speed operation?
Yes, the LPC55S16JEV98K supports crystal-less USB full-speed device operation using its internal 48 MHz FRO clock, eliminating the need for an external 12 MHz crystal. This capability is implemented in the on-chip USB FS PHY and validated in NXP technical note TN00065. The LPC55S16JEV98K retains full-speed host/device functionality without external timing components.
What is the role of the PRINCE module in the LPC55S16JEV98K?
The PRINCE module in the LPC55S16JEV98K performs real-time AES-128 encryption of data written to on-chip flash and decryption of encrypted data during read - transparently protecting firmware assets without CPU intervention. It enables secure over-the-air updates and prevents reverse engineering of flash contents. The LPC55S16JEV98K uses PRINCE to safeguard application code, configuration data, and cryptographic keys stored in flash.
How many ADC channels does the LPC55S16JEV98K support, and what is its maximum sampling rate?
The LPC55S16JEV98K integrates a 16-bit successive-approximation ADC with five differential channel pairs (or ten single-ended inputs), supporting simultaneous conversions on paired channels. Its maximum sampling rate is 2.0 Msamples/sec, enabled by dedicated hardware triggers and DMA-driven data transfer. The LPC55S16JEV98K also includes an integrated temperature sensor connected directly to this ADC subsystem.
What package type is used for the LPC55S16JEV98K, and what are its key mechanical dimensions?
The LPC55S16JEV98K uses the VFBGA98 package (SOT1982-1): a 98-ball thin fine-pitch ball grid array with 7 mm × 7 mm body size, 0.5 mm height, and 0.4 mm ball pitch. It features an exposed thermal pad for enhanced heat dissipation and complies with JEDEC MO-277 standards. The LPC55S16JEV98K's VFBGA98 footprint is identical to other LPC55S1x variants in the same package variant.
LPC55S16JEV98K Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 98-VFBGA
- Series:
- LPC55S1x
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit Single-Core
- Speed:
- 150MHz
- Connectivity:
- CAN FD, Flexcomm, I2C, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, PWM, RNG, WDT
- Number of I/O:
- 64
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 96K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 10x16b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC55S16JEV98K FAQ
1.How can I place an order for LPC55S16JEV98K through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC55S16JEV98K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC55S16JEV98K reliable?
The price and inventory of LPC55S16JEV98K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC55S16JEV98K is usually 5 days.
3.What payment methods are accepted for LPC55S16JEV98K?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC55S16JEV98K transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC55S16JEV98K?
LPC55S16JEV98K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC55S16JEV98K order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC55S16JEV98K?
For technical support, including LPC55S16JEV98K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC55S16JEV98K requirements.
6.How does Aetrix verify that LPC55S16JEV98K is sourced from the original manufacturer or authorized distributors?
All LPC55S16JEV98K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC55S16JEV98K meets industry standards.
7.What is the process for return or replacement of LPC55S16JEV98K?
All LPC55S16JEV98K units undergo pre-shipment inspection (PSI). If there is an issue with LPC55S16JEV98K, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC55S16JEV98K part is unused and in its original packaging.
Return procedure for LPC55S16JEV98K:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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