NXP Semiconductors LPC55S26JBD100Y

Overview

LPC55S26JBD100 from NXP Semiconductors is a 32-bit Arm Cortex-M33 microcontroller with secure boot, PRINCE flash encryption, CASPER crypto co-processor, 256 KB on-chip flash, 144 KB SRAM, and dual USB (FS + HS) support. It operates up to 150 MHz and targets secure IoT edge nodes, industrial control gateways, and trusted firmware update systems.

For engineers reviewing the LPC55S26JBD100 datasheet, LPC55S26JBD100 pinout, LPC55S26JBD100 application, or LPC55S26JBD100 equivalent, key selection criteria include flash/SRAM capacity, PRINCE/PUF/AES-256 security features, HLQFP100 package compatibility, and Flexcomm peripheral configurability for mixed-protocol communication stacks.

Technical Context

The LPC55S26JBD100 implements Arm TrustZone for hardware-isolated secure/non-secure execution environments, with dedicated secure boot ROM verifying RSA-2048/4096 signatures of SHA256-hashed images. Its CASPER engine accelerates ECC operations including P-256 and P-384 curves, while PRINCE performs real-time AES-128 encryption/decryption of flash reads and writes.

It integrates two DMA controllers (23-channel DMA0 and 10-channel DMA1), nine Flexcomm interfaces supporting USART/SPI/I2C/I2S in software-defined roles, and a programmable logic unit (PLU) for glue logic offload. The 16-bit 1.0 Msamples/sec ADC supports simultaneous differential conversions across five channel pairs, synchronized with internal timers or external triggers.

Key Specifications

Pinout & Package

Package: HLQFP100 - plastic low-profile quad flat package with 100 leads, body size 14 × 14 × 0.5 mm, 0.5 mm pitch, lead finish matte tin.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar secure microcontroller applications.

Compared with LPC55S26JBD100, LPC55S28JBD100 offers double flash/SRAM for larger applications without altering pinout or security architecture, while LPC5526JBD100 removes all hardware security blocks-making it unsuitable for certified secure deployments but viable for legacy-compatible cost-down.

Availability

LPC55S26JBD100 is available at Aetrix Electronics and suitable for industrial automation, medical diagnostics, and smart energy metering requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for LPC55S26JBD100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in Arm-based microcontrollers and hardware security IP.

The LPC55S2x product line was designed for resource-constrained edge devices requiring certified security (TBSA), real-time performance, and flexible peripheral routing-enabling rapid development of trustworthy embedded systems.

FAQ

What security certifications does the LPC55S26JBD100 support?

The LPC55S26JBD100 implements Arm TrustZone and complies with the PSA Certified Level 3 and TBSA (Trusted Board Startup Architecture) specifications. It supports secure boot with RSA-2048/4096 signature verification, PRINCE flash encryption, and PUF-based key derivation-all validated in NXP's official security documentation. These features enable certification paths for IEC 62443 and Common Criteria EAL4+ in end-system evaluations. The LPC55S26JBD100 itself is not individually certified, but its hardware primitives form the foundation for certified implementations.

Does the LPC55S26JBD100 support crystal-less USB full-speed operation?

Yes, the LPC55S26JBD100 supports crystal-less USB full-speed device mode using its internal 48 MHz clock derived from the FRO and calibrated via software library (TN00063). This eliminates the need for an external 12 MHz crystal in FS-only applications, reducing BOM cost and board space. Crystal-less operation is not supported for USB high-speed mode, which requires an external 12 MHz reference clock for PHY lock.

How many Flexcomm interfaces can operate simultaneously as I2C in the LPC55S26JBD100?

The LPC55S26JBD100 includes nine Flexcomm interfaces (FC0–FC8), of which FC0–FC7 can be independently configured as I2C-including Fast-mode Plus (1 Mbit/s) and high-speed slave mode (3.4 Mbit/s). All eight are fully functional concurrently, with separate clock domains and FIFOs. FC8 is dedicated to high-speed SPI and cannot be used as I2C. Each I2C instance supports multiple address recognition and monitor mode, enabling multi-master arbitration and debug snooping.

What is the maximum ADC sampling rate achievable with simultaneous differential conversion on the LPC55S26JBD100?

The LPC55S26JBD100's 16-bit ADC achieves a maximum sampling rate of 1.0 Msamples/sec when performing simultaneous conversions on two channels belonging to the same differential pair (e.g., CH1A and CH1B). This rate is sustained under continuous conversion mode with internal trigger sources such as timers or PWM events. External triggers may introduce minor jitter but do not reduce the per-channel throughput, as the ADC hardware supports interleaved sampling without pipeline stalls.

Can the PRINCE module encrypt only specific regions of flash memory on the LPC55S26JBD100?

Yes, the PRINCE module in the LPC55S26JBD100 supports region-based encryption: flash is divided into 16 configurable regions (each 32 KB), and each region can be independently enabled for real-time AES-128 encryption/decryption. This allows selective protection of bootloader, secure firmware, or configuration data while leaving non-sensitive application code unencrypted-optimizing performance and enabling partial updates without decrypting the entire flash array. Region mapping is controlled via protected flash registers (PFR).