NXP Semiconductors LPC55S26JBD64K

Overview

LPC55S26JBD64K from NXP is a dual-core Arm Cortex-M33 microcontroller operating at up to 150 MHz with 256 KB on-chip flash, 144 KB SRAM, and integrated security features including AES-256, SHA-2, SRAM PUF, and PRINCE real-time encryption-designed for secure industrial IoT edge nodes requiring authenticated boot and encrypted firmware execution.

For engineers reviewing the LPC55S26JBD64K datasheet, LPC55S26JBD64K pinout, LPC55S26JBD64K application, or LPC55S26JBD64K equivalent, key selection considerations include its HTQFP64 package, dual M33 cores with TrustZone *not supported*, FlexComm interface configurability (UART/SPI/I²C/I²S), USB HS/FS PHY integration, and mandatory secure debug authentication via PFR and UID.

Technical Context

The LPC55S26JBD64K implements two Arm Cortex-M33 cores without TrustZone, sharing a unified memory map and clocked by a configurable System PLL up to 150 MHz. It integrates a dedicated Crypto Engine supporting AES-256/SHA-2 acceleration and PRINCE for transparent flash decryption during execution.

Its analog subsystem includes a 16-bit 1 MSPS ADC, ACMP, and on-die temperature sensor; digital peripherals include 8 FlexComm units (each configurable as UART/SPI/I²C/I²S), SDIO, HS/FS USB with embedded PHY, and a programmable logic unit (6-input, 8-output) for glue logic offload.

Key Specifications

Pinout & Package

Package: HTQFP64 (64-pin, 10 mm × 10 mm, 0.5 mm pitch, exposed thermal pad).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core secure microcontroller applications.

Compared with LPC55S26JBD64K, LPC55S28JBD64K offers double flash/SRAM for scalable firmware while retaining identical security architecture; RA6M5GFP100CH00 provides TrustZone-based isolation but requires external key provisioning and lacks PUF/PRINCE-making it less suitable for zero-touch secure deployment.

Availability

LPC55S26JBD64K is available at Aetrix Electronics and suitable for industrial IoT edge nodes, secure diagnostic tools, and smart building controllers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for LPC55S26JBD64K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.

The LPC55S26JBD64K belongs to NXP's LPC5500 series-a mainstream Arm Cortex-M33 MCU family engineered for cost-sensitive, security-critical embedded applications where energy efficiency, peripheral integration, and hardware-rooted trust are essential.

FAQ

Does LPC55S26JBD64K support Arm TrustZone technology?

No, the LPC55S26JBD64K explicitly does not support Arm TrustZone. This is confirmed in the official LPC552xFAMFS document revision 1, which states "LPC55S2x/2x does not support Arm TrustZone technology." Security isolation relies instead on NXP's proprietary PFR, secure debug enforcement, and memory protection unit (MPU) configuration-making LPC55S26JBD64K appropriate for applications requiring hardware-rooted security without TrustZone dependency.

What is the maximum clock frequency and core configuration of LPC55S26JBD64K?

The LPC55S26JBD64K operates at up to 150 MHz using two Arm Cortex-M33 cores without floating-point units enabled by default. Both cores share the same memory map and clock domain, and each supports SIMD instructions. The System PLL generates the core clock, and the USB PLL provides dedicated timing for high-speed USB operation-enabling deterministic real-time response in dual-core configurations.

How does the PRINCE engine function in LPC55S26JBD64K?

The PRINCE engine in LPC55S26JBD64K performs real-time AES-128 decryption of encrypted flash contents during instruction fetch-without requiring decrypted code to reside in SRAM. This allows LPC55S26JBD64K to execute firmware directly from encrypted flash, reducing attack surface and eliminating RAM-based decryption overhead. PRINCE keys are derived from the SRAM PUF and protected by the PFR, ensuring that decryption only occurs under authenticated boot conditions.

Which development boards are compatible with LPC55S26JBD64K?

The LPCXpresso55S28 Development Board (LPC55S28-EVK) is fully compatible with LPC55S26JBD64K due to pin, peripheral, and software compatibility within the LPC55S2x family. It features onboard Link2 debug probe, Arduino®/Mikroe headers, and direct support in MCUXpresso IDE-allowing rapid evaluation of LPC55S26JBD64K's FlexComm, USB, and security features without hardware modification.

What security features are unique to LPC55S26JBD64K compared to standard Cortex-M33 MCUs?

LPC55S26JBD64K integrates several hardware security features uncommon in generic Cortex-M33 MCUs: SRAM PUF for unclonable key generation, PRINCE for real-time encrypted flash execution, dedicated Crypto Engine for AES-256/SHA-2 acceleration, and PFR-enforced secure debug authentication. These features collectively establish a hardware-rooted chain of trust absent in most competitive offerings-making LPC55S26JBD64K especially suited for zero-touch provisioning and firmware IP protection.