NXP Semiconductors LPC55S26JEV98K

Overview

LPC55S26JEV98K from NXP is a secure Arm Cortex-M33 microcontroller operating at up to 150 MHz with 256 KB flash, 144 KB SRAM, and integrated AES-256/SHA-2 crypto acceleration, deployed in industrial IoT gateways requiring real-time control and firmware integrity verification.

For engineers reviewing the LPC55S26JEV98K datasheet, LPC55S26JEV98K pinout, LPC55S26JEV98K application, or LPC55S26JEV98K equivalent, key selection criteria include VFBGA98 package compatibility, SRAM PUF-based root-of-trust provisioning, PRINCE on-the-fly decryption support, and FlexComm interface configurability across UART/SPI/I²C/I²S.

Technical Context

The LPC55S26JEV98K implements an Arm Cortex-M33 core with TrustZone disabled (per NXP documentation), FPU and SIMD support, and dual DMA controllers (22-channel DMA0 + 10-channel DMA1) for concurrent peripheral data movement. It integrates a dedicated ROM bootloader (128 KB) supporting USB and serial ISP, alongside hardware-accelerated cryptographic functions including AES-256, SHA-2, and PRINCE real-time encrypted execution.

Security architecture centers on SRAM PUF for device-unique key generation and provisioning, complemented by secure debug disable, Protected Flash Region (PFR), and UID enforcement. Clocking includes System PLL, USB PLL, and multiple oscillator sources, enabling precise timing for USB HS/FS, SDIO, and high-speed SPI operation.

Key Specifications

Pinout & Package

VFBGA98 package: 98-ball very thin fine-pitch ball grid array, 9 mm × 9 mm body, 0.8 mm ball pitch, 0.35 mm ball diameter, standard JEDEC MO-277 compliant footprint.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar secure microcontroller applications.

Compared with LPC55S26JEV98K, the LPC55S28JEV98K provides headroom for future firmware expansion and multi-image secure boot, while the LPC55S16JEV98K reduces bill-of-materials cost where memory constraints permit tighter optimization.

Availability

LPC55S26JEV98K is available at Aetrix Electronics and suitable for industrial IoT gateways, medical diagnostic interfaces, and building automation controllers requiring stable component supply over extended production lifecycles.

Supply support for LPC55S26JEV98K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.

The LPC55Sxx product line delivers Arm Cortex-M33-based MCUs optimized for embedded applications demanding hardware-enforced security, real-time responsiveness, and high peripheral integration without external PMIC or crypto co-processors.

FAQ

What is the maximum operating frequency of the LPC55S26JEV98K?

The LPC55S26JEV98K operates at a maximum CPU frequency of 150 MHz. This performance level is sustained across its full industrial temperature range (–40°C to +105°C) when powered from its nominal 3.3 V supply. The Arm Cortex-M33 core includes floating-point unit and SIMD extensions, enabling efficient execution of control algorithms and signal processing tasks without external accelerators. All timing-critical peripherals-including USB HS, SDIO, and FlexComm interfaces-are fully functional at this clock rate.

Does the LPC55S26JEV98K support Arm TrustZone technology?

No, the LPC55S26JEV98K does not support Arm TrustZone technology. NXP explicitly states in the LPC552xFAMFS datasheet that "LPC55S2x/2x does not support Arm TrustZone technology." Security isolation is instead implemented through alternative hardware mechanisms including SRAM PUF, Protected Flash Region (PFR), PRINCE on-the-fly decryption, and secure debug disable-providing robust, silicon-rooted protection without TrustZone.

What package type is used for the LPC55S26JEV98K?

The LPC55S26JEV98K uses a VFBGA98 package: a 9 mm × 9 mm very thin fine-pitch ball grid array with 98 solder balls arranged in a 10 × 10 grid (corner balls omitted), 0.8 mm pitch, and JEDEC MO-277 compliance. This package supports high-density PCB layouts and thermal performance suitable for fanless industrial enclosures. Pin-compatible variants include HLQFP100 and HTQFP64, but LPC55S26JEV98K specifically denotes the VFBGA98 option.

How is secure boot implemented on the LPC55S26JEV98K?

Secure boot on the LPC55S26JEV98K relies on immutable ROM bootloader validation using SHA-2 hash and RSA-2048 signature verification. Boot images must be signed and placed in designated flash regions protected by PFR. The process enforces chain-of-trust from reset vector through initial firmware load. SRAM PUF-derived keys can optionally seal private keys used in the signing process, ensuring firmware authenticity and preventing rollback attacks without external key storage.

Can the LPC55S26JEV98K operate without external crystals?

Yes, the LPC55S26JEV98K can operate without external crystals. It includes internal RC oscillators (IRC) for startup and low-power modes, and supports internal FRO (Free Running Oscillator) at 12 MHz, 48 MHz, and 96 MHz. While external crystals (e.g., 12 MHz or 32.768 kHz) are recommended for USB HS timing accuracy and RTC precision, the internal FRO enables full functionality-including USB FS, UART, and ADC-for prototyping and cost-sensitive designs where ±1% frequency tolerance is acceptable.