NXP Semiconductors LPC55S26JEV98Y

Overview

LPC55S26JEV98Y from NXP Semiconductors is a 32-bit Arm Cortex-M33 microcontroller with hardware-accelerated cryptography (CASPER), 256 KB on-chip flash, 144 KB SRAM, PRINCE real-time flash encryption, and dual USB (FS + HS) support. It operates up to 150 MHz and targets secure IoT edge nodes requiring certified boot, tamper-resistant key storage, and low-power operation in industrial temperature range (−40 °C to +105 °C).

For engineers reviewing the LPC55S26JEV98Y datasheet, LPC55S26JEV98Y pinout, LPC55S26JEV98Y application, or LPC55S26JEV98Y equivalent, this page delivers verified technical context, validated pin functions for VFBGA98, security feature mapping, and direct alternative comparisons - all grounded in Rev. 2.3 (29 August 2024) official documentation.

Technical Context

The LPC55S26JEV98Y implements an Arm Cortex-M33 core (r0p3) with MPU, FPU, DSP, and ETM, running at up to 150 MHz. Its CASPER co-processor accelerates ECC and FFT operations, while PRINCE enables real-time AES-256 encryption/decryption of flash contents without software overhead.

Security architecture includes PUF-based key generation (64–4096 bits), SHA2/AES hardware engine, RSA-2048/4096 secure boot verification, and debug authentication via NXP Debug Authentication Protocol v1.0/v1.1. The device supports boot from PRINCE-encrypted flash regions and sealed-part fault analysis mode.

Key Specifications

Pinout & Package

VFBGA98 package (SOT1982-1) with 98 balls, 0.5 mm pitch, 7 mm × 7 mm body size. Pin functions are software-selectable via IOCON registers; default reset state disables most pull-ups/pull-downs except specific debug and boot pins (e.g., PIO0_5 determines boot source).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar secure microcontroller applications.

Compared with LPC55S28JEV98, the LPC55S26JEV98Y trades flash/SRAM capacity for cost-sensitive deployments while retaining identical security primitives; versus RA6M5GFP, it delivers stronger silicon-rooted trust via PUF and PRINCE at the expense of general-purpose memory headroom.

Availability

LPC55S26JEV98Y is available at Aetrix Electronics and suitable for industrial sensor nodes, secure gateways, medical wearables, smart energy meters, and automotive body electronics requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for LPC55S26JEV98Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in Arm-based microcontrollers and trusted execution environments.

The LPC55S2x series was designed specifically for resource-constrained, security-critical edge devices - integrating hardware-enforced trust (PUF, PRINCE, CASPER) with real-time performance and low-power operation in a single chip.

FAQ

What is the maximum operating frequency of the LPC55S26JEV98Y?

The LPC55S26JEV98Y runs at a maximum CPU frequency of 150 MHz. This is achieved using PLL0 or PLL1, which can be clocked from the internal 12 MHz FRO, external crystal (16–32 MHz), or 32.768 kHz RTC oscillator. The core includes an FPU and DSP extensions, enabling deterministic execution of floating-point and signal-processing workloads within this timing budget. The LPC55S26JEV98Y maintains this frequency across its full industrial temperature range (−40 °C to +105 °C).

Does the LPC55S26JEV98Y support secure boot with public-key verification?

Yes, the LPC55S26JEV98Y supports secure boot using RSASSA-PKCS1-v1_5 signatures of SHA256 digests, with RSA-2048 and RSA-4096 public keys. It validates image signatures against up to four revocable Root-of-Trust keys stored as SHA-256 hashes in protected flash. The LPC55S26JEV98Y also enforces anti-rollback via serial-number-based image key revocation and supports NXP Secure Boot file format (SB2 v2.0) for authenticated firmware loading.

What package type and pin count does the LPC55S26JEV98Y use?

The LPC55S26JEV98Y uses a VFBGA98 package (SOT1982-1) with 98 balls, 0.5 mm pitch, and a 7 mm × 7 mm body size. This fine-pitch BGA is optimized for compact industrial and portable designs. Pin functions are configurable via IOCON registers, and the device shares identical pinout with other VFBGA98 variants in the LPC55S2x family, including LPC55S28JEV98 and LPC5526JEV98.

How does the PRINCE module function in the LPC55S26JEV98Y?

The PRINCE module in the LPC55S26JEV98Y performs real-time AES-256 encryption of data written to on-chip flash and decryption of encrypted data during read operations - all transparent to software. Keys are derived from the PUF or supplied by firmware, and the engine operates inline with flash controller transactions. This enables secure firmware IP protection and safe over-the-air updates without exposing decrypted code in memory. The LPC55S26JEV98Y supports booting directly from PRINCE-encrypted flash regions.

Which analog peripherals are integrated into the LPC55S26JEV98Y?

The LPC55S26JEV98Y integrates a 16-bit, 1.0 Msamples/sec ADC with five differential or ten single-ended input channels, an analog comparator with five inputs and selectable internal/external reference, and an on-die temperature sensor connected to the ADC. These peripherals share dedicated analog power domains (VDDA/VSSA) and support hardware-triggered conversions via timers or external events - enabling synchronized, high-precision sensor acquisition without CPU polling. The LPC55S26JEV98Y's ADC achieves <±1 LSB INL under specified conditions.