NXP Semiconductors LPC55S28JBD100E

Overview

LPC55S28JBD100E from NXP Semiconductors is a 32-bit Arm Cortex-M33 microcontroller with CASPER crypto co-processor, 512 KB flash, 256 KB SRAM, PRINCE real-time flash encryption, and dual USB (FS + HS) support-designed for secure industrial edge nodes requiring cryptographic acceleration, low-power operation, and robust peripheral integration.

For engineers reviewing the LPC55S28JBD100E datasheet, LPC55S28JBD100E pinout, LPC55S28JBD100E application, or LPC55S28JBD100E equivalent, key selection considerations include its 150 MHz CPU frequency, PUF-based key generation, 64 GPIOs in HLQFP100 package, and support for secure boot with RSA-2048/4096 and SHA256 signature verification.

Technical Context

The LPC55S28JBD100E implements a dual-bus AHB matrix architecture with separate code and system buses, enabling concurrent flash access and DMA transfers. Its CASPER engine offloads ECC, RSA, and FFT operations from the Cortex-M33 core while maintaining deterministic latency.

Security is enforced at silicon level via PRINCE (on-the-fly encrypted flash), PUF-derived keys, AES-256/SHA2 hardware accelerators, and debug authentication using NXP's RSA-2048/4096 protocol. The device supports TBSA-compliant secure boot with up to four revocable Root of Trust keys stored in protected flash.

Key Specifications

Pinout & Package

Package: HLQFP100 - plastic low-profile quad flat package with 100 leads, body size 14 × 14 × 0.5 mm, 0.5 mm pitch, lead finish matte tin.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar secure microcontroller applications.

Compared with LPC55S69JBD100E and STM32H743VIT6, the LPC55S28JBD100E delivers best-in-class balance of cryptographic hardware (PUF, PRINCE, CASPER), low-power design, and peripheral configurability for secure embedded applications below 150 MHz real-time requirements.

Availability

LPC55S28JBD100E is available at Aetrix Electronics and suitable for industrial PLC edge nodes, secure IoT gateways, medical wearable hubs, and smart energy meters requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for LPC55S28JBD100E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.

The LPC55S2x series targets secure, low-power edge intelligence applications-designed to integrate cryptographic acceleration, flexible peripherals, and robust power management into a single chip for trusted embedded systems.

FAQ

What is the maximum operating frequency of the LPC55S28JBD100E?

The LPC55S28JBD100E operates at a maximum CPU frequency of 150 MHz, achieved via PLL0 or PLL1 driven by internal FRO (12 MHz), external crystal (16–32 MHz), or RTC oscillator (32.768 kHz). This frequency is sustained across the full -40 °C to +105 °C temperature range with appropriate voltage regulation.

Does the LPC55S28JBD100E support secure boot with hardware-enforced root of trust?

Yes, the LPC55S28JBD100E implements TBSA-compliant secure boot using RSASSA-PKCS1-v1_5 signatures over SHA256 digests. It stores up to four revocable Root of Trust public key hashes in protected flash and supports anti-rollback via x509 certificate serial number–based image key revocation-enabling hardware-enforced chain of trust.

What package type and pin count does the LPC55S28JBD100E use?

The LPC55S28JBD100E uses the HLQFP100 package: a 100-lead, low-profile quad flat package with 14 × 14 × 0.5 mm body dimensions and 0.5 mm pitch (SOT1570-3). This package provides 64 GPIOs, multiple power/ground pins, and dedicated debug and USB PHY routing capability.

How does the PRINCE module function in the LPC55S28JBD100E?

The PRINCE module in the LPC55S28JBD100E performs real-time AES-128 encryption during flash writes and decryption during reads-transparently protecting firmware assets without software intervention. It operates on 64-bit blocks and requires no CPU cycles, enabling secure OTA updates and intellectual property protection with zero runtime overhead.

Can the LPC55S28JBD100E operate without an external crystal?

Yes, the LPC55S28JBD100E can operate fully crystal-less using its internal Free Running Oscillators (FROs): a 96 MHz FRO (±2% accuracy over -40 °C to +105 °C) for main system clock and a 32 kHz FRO for RTC. USB full-speed device mode also supports crystal-less operation via software timing calibration per TN00063.