NXP Semiconductors LPC55S28JBD100K

Overview

LPC55S28JBD100K from NXP is a dual-core Arm Cortex-M33 microcontroller operating at up to 150 MHz with 512 KB on-chip flash, 256 KB SRAM, and integrated PRINCE real-time encryption engine, AES-256/SHA-2 crypto accelerator, and SRAM PUF for secure boot and provisioning - deployed in industrial IoT gateways requiring trusted firmware execution and tamper-resistant device identity.

For engineers reviewing the LPC55S28JBD100K datasheet, LPC55S28JBD100K pinout, LPC55S28JBD100K application, or LPC55S28JBD100K equivalent, key selection considerations include its dual M33 core support (one with TrustZone disabled), FlexComm interface configurability (UART/SPI/I²C/I²S), HS/FS USB with PHY, SDIO host capability, and HLQFP100 package with 100-pin 0.5 mm pitch layout.

Technical Context

The LPC55S28JBD100K implements two Arm Cortex-M33 cores without TrustZone, each with FPU and SIMD support, sharing system resources including memory controllers, DMA engines (DMA0: 22-channel, DMA1: 10-channel), and clock generation (System PLL + USB PLL). It integrates a dedicated ROM bootloader (128 KB) supporting in-system flash programming via UART, USB, or SPI.

Security architecture includes hardware-accelerated AES-256/SHA-2, PRINCE for on-the-fly encrypted flash execution, SRAM PUF for unique device key derivation, and secure debug authentication enforced by PFR and UID registers - all verified under NXP's LPC552xFAMFS Rev 1 specification.

Key Specifications

Pinout & Package

Package: HLQFP100 (100-pin, 0.5 mm pitch, exposed thermal pad).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar secure microcontroller applications.

Compared with LPC55S28JBD100K, LPC55S69JBD100K provides stronger isolation via TrustZone but requires firmware rearchitecture, while RA6M5GFP100AA00 offers greater raw performance and memory headroom at the cost of integrated hardware security features essential for zero-trust edge deployments.

Availability

LPC55S28JBD100K is available at Aetrix Electronics and suitable for industrial IoT gateways, secure edge nodes, and building automation controllers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for LPC55S28JBD100K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.

The LPC55S28JBD100K belongs to NXP's LPC552x family - designed specifically for cost-sensitive, security-critical embedded applications demanding hardware-rooted trust, real-time responsiveness, and high peripheral integration without external components.

FAQ

What is the maximum operating frequency of the LPC55S28JBD100K?

The LPC55S28JBD100K operates at up to 150 MHz on both Arm Cortex-M33 cores. This frequency is sustained under full voltage and temperature specifications per NXP's LPC552xFAMFS Rev 1 datasheet, with System PLL and USB PLL enabling independent clock domains for peripherals and USB functionality. The LPC55S28JBD100K maintains deterministic timing at this rate across all supported low-power modes.

Does the LPC55S28JBD100K support TrustZone technology?

No, the LPC55S28JBD100K does not support Arm TrustZone. According to NXP's official documentation (LPC552xFAMFS Rev 1), TrustZone is explicitly excluded from the LPC55S2x series. Security isolation relies instead on PRINCE, SRAM PUF, and PFR-based debug lockdown - making the LPC55S28JBD100K appropriate for applications requiring hardware-enforced encryption and device identity without full TrustZone world separation.

What package type is used for the LPC55S28JBD100K?

The LPC55S28JBD100K uses the HLQFP100 package: a 100-pin, thermally enhanced low-profile quad flat pack with 0.5 mm pitch and exposed thermal pad. This package is pin-compatible with other LPC552x variants in the same footprint (e.g., LPC55S26JBD100K), enabling design reuse across memory/configurations while maintaining mechanical and thermal compatibility in industrial PCB layouts.

How does the PRINCE engine function in the LPC55S28JBD100K?

The PRINCE engine in the LPC55S28JBD100K performs real-time AES-128 decryption of flash contents during instruction fetch, allowing secure code execution directly from encrypted memory. It operates transparently to software, requires no runtime CPU overhead, and supports key provisioning via SRAM PUF - ensuring that the LPC55S28JBD100K can run authenticated, encrypted firmware images without exposing plaintext code in memory or flash.

Can the LPC55S28JBD100K support simultaneous USB and SDIO operations?

Yes, the LPC55S28JBD100K supports concurrent HS/FS USB and SDIO host operations. Its dedicated USB PHY and separate SDIO controller operate on independent clock domains (USB PLL vs. System PLL), and share no critical memory or DMA resources. Verified in NXP's MCUXpresso SDK examples, the LPC55S28JBD100K reliably handles USB CDC ACM communication while streaming data from microSD cards - a capability confirmed in LPC552xFAMFS Rev 1 timing and resource allocation tables.