NXP Semiconductors LPC55S28JBD100Y

Overview

LPC55S28JBD100Y from NXP Semiconductors is a 32-bit Arm Cortex-M33 microcontroller with CASPER crypto co-processor, 512 KB flash, 256 KB SRAM, PRINCE real-time flash encryption, and dual USB (FS + HS) support - deployed in secure industrial gateways requiring cryptographic acceleration, OTA firmware updates, and low-power operation.

For engineers reviewing the LPC55S28JBD100Y datasheet, LPC55S28JBD100Y pinout, LPC55S28JBD100Y application, or LPC55S28JBD100Y equivalent, key selection criteria include secure boot compliance (RSA-2048/4096), 150 MHz CPU performance, 64 GPIOs with secure I/O capability, and HLQFP100 package compatibility for high-pin-count embedded control designs.

Technical Context

The LPC55S28JBD100Y integrates an Arm Cortex-M33 core with MPU, FPU, DSP, and ETM, running at up to 150 MHz with memory protection and secure debug authentication. Its CASPER engine accelerates ECC and FFT operations, while PRINCE enables transparent on-the-fly encryption/decryption of flash contents.

Security architecture includes PUF-based key generation (64–4096 bits), AES-256, SHA2, TRNG, and TBSA-compliant secure boot using x.509 certificates and revocable RoT keys. Clocking combines FRO (±1% accuracy, 0°C–85°C), crystal oscillators (16–32 MHz & 32.768 kHz), and dual PLLs for flexible system timing.

Key Specifications

Pinout & Package

Package: HLQFP100 (plastic low-profile quad flat package, 100 leads, body 14 × 14 × 0.5 mm, pitch 0.5 mm, SOT1570-3).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar secure microcontroller applications.

Compared with LPC55S28JBD100Y, LPC55S69JBD100 offers greater memory headroom and dual-core flexibility at the expense of PRINCE, while RA6M5GFP100FB trades CASPER and PRINCE for CAN FD and safety certification - making LPC55S28JBD100Y optimal for cost-sensitive, flash-encryption-dependent industrial edge nodes.

Availability

LPC55S28JBD100Y is available at Aetrix Electronics and suitable for industrial IoT gateways, secure medical sensor hubs, smart energy meters, and automotive body control modules requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for LPC55S28JBD100Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with R&D centers across Europe, Asia, and North America.

The LPC55S2x series targets high-assurance embedded applications demanding hardware-rooted security, cryptographic acceleration, and low-power operation - designed specifically for secure edge intelligence where firmware integrity and runtime protection are non-negotiable.

FAQ

What is the maximum CPU frequency supported by the LPC55S28JBD100Y?

The LPC55S28JBD100Y operates at a maximum CPU frequency of 150 MHz, enabled by its Arm Cortex-M33 core and supported by internal PLLs that accept input from the 12 MHz FRO, external crystal (16–32 MHz), or 32.768 kHz RTC oscillator. This frequency is sustained across the full -40°C to +105°C operating range with appropriate voltage regulation.

Does the LPC55S28JBD100Y support secure boot with revocable root-of-trust keys?

Yes, the LPC55S28JBD100Y supports secure boot with up to four revocable Root of Trust (RoT) keys stored as SHA-256 hash digests in protected flash. It uses RSASSA-PKCS1-v1_5 signatures over SHA256 image digests and supports x.509 certificate validation, enabling field-upgradable trust anchors and anti-rollback enforcement via image key revocation.

How does the PRINCE module function in the LPC55S28JBD100Y?

The PRINCE module in the LPC55S28JBD100Y performs real-time AES-128 encryption of data written to on-chip flash and decryption of encrypted data read from flash. It operates transparently without CPU involvement, protecting application code and enabling secure over-the-air updates - all while maintaining full flash performance and wear-leveling compatibility.

What analog capabilities does the LPC55S28JBD100Y provide?

The LPC55S28JBD100Y integrates a 16-bit ADC with simultaneous sampling on differential pairs, supporting up to 1.0 Msamples/sec. It includes five differential channel pairs (10 single-ended inputs), internal/external trigger sources, and an integrated temperature sensor. A dedicated analog comparator with five inputs and selectable reference completes its analog front-end.

Is the LPC55S28JBD100Y compatible with crystal-less USB full-speed device operation?

Yes, the LPC55S28JBD100Y supports crystal-less USB 2.0 full-speed device operation using its internal 96 MHz FRO and software library examples (e.g., TN00063). This eliminates the need for an external 12 MHz crystal in USB peripheral designs, reducing BOM cost and board space while maintaining USB compliance.