NXP Semiconductors LPC55S28JBD64E
- Part No.:
- LPC55S28JBD64E
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 64-TQFP Exposed Pad
- Datasheet:
-
LPC55S28JBD64E.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 64TQFP
- Quantity:
- Payment:

- Shipping:

Inventory:160
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Product details
Overview
LPC55S28JBD64E from NXP Semiconductors is a 32-bit Arm Cortex-M33 microcontroller with CASPER crypto co-processor, 512 KB flash, 256 KB SRAM, PRINCE real-time flash encryption, and dual USB (FS + HS) support-designed for secure industrial edge nodes requiring cryptographic acceleration and low-power operation.
For engineers reviewing the LPC55S28JBD64E datasheet, LPC55S28JBD64E pinout, LPC55S28JBD64E application, or LPC55S28JBD64E equivalent, this page delivers verified technical context, package-specific pin mapping, security feature implementation details, and validated alternative options for secure MCU selection in resource-constrained embedded systems.
Technical Context
The LPC55S28JBD64E implements Arm TrustZone for Armv8-M to isolate secure and non-secure execution environments, with hardware-enforced memory protection via MPU and dedicated secure boot ROM supporting RSA-2048/4096 signature verification. Its CASPER engine accelerates ECC operations including point multiplication over NIST P-256 and P-384 curves.
It integrates two independent USB controllers-one full-speed (FS) with crystal-less device mode and one high-speed (HS) with on-chip PHY-alongside nine Flexcomm interfaces configurable as USART/SPI/I²C/I²S, enabling concurrent multi-protocol connectivity without external transceivers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 @ 150 MHz with FPU, DSP, ETM, and TrustZone security extension |
| Flash Memory | 512 KB on-chip flash with PRINCE real-time encryption/decryption and 512-byte page erase |
| SRAM | 256 KB total: 32 KB code bus, 208 KB system bus (192 KB contiguous), 16 KB USB-dedicated SRAM |
| Security Features | CASPER crypto co-processor, PUF-based key generation (64–4096 bits), TRNG, SHA2-AES engine, secure GPIO, debug authentication (RSA-2048/4096) |
| Analog Peripherals | 16-bit ADC @ 1.0 Msamples/sec with simultaneous dual-channel conversion, 5 differential/10 single-ended inputs, integrated temp sensor, comparator |
| Serial Interfaces | Nine Flexcomm peripherals (FC0–FC8); FC0–FC7 configurable as USART/SPI/I²C/I²S; FC8 dedicated high-speed SPI; dual USB (FS + HS) with on-chip PHY |
| Timers & PWM | Five 32-bit general-purpose timers, SCTimer/PWM (8 inputs/10 outputs), RTC with 1 s resolution and wake-up from deep power-down, MRT, WWDT |
| Package & Pins | HTQFP64 (10 × 10 × 0.5 mm, 0.4 mm pitch); 36 GPIOs, 8 pin-interrupt-capable pins, 2 GPIO group interrupts (GINT) |
Pinout & Package
HTQFP64 package (SOT855-5) with exposed thermal pad, 64 leads, 0.4 mm pitch, 10 mm × 10 mm body. Pin functions are software-selectable via IOCON registers; default reset state includes internal pull-up on PIO0_5 and PIO0_12, pull-down on PIO0_2 and PIO0_11.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PIO0_0 / ACMP0_A | GPIO / Analog Comparator Input A | Dual-role pin: digital I/O by default; analog comparator input when ANAMODE=1 and DIGIMODE=0 in IOCON |
| PIO0_5 / TDI | Test Data In / Boot Source Selector | JTAG boundary scan input; boot source (flash/ISP) determined by logic level at reset |
| FC3_SCK | Flexcomm 3 Clock | Shared clock for USART/SPI/I²S operation on Flexcomm 3; supports fractional baud rate generation |
| SD0_CMD | SD/MMC 0 Command Line | Bi-directional command interface for SDIO/SD/MMC card slot; supports SDR25 (52 MHz) timing |
| USB0_DP / USB0_DM | USB Full-Speed Differential Pair | On-chip FS PHY interface; crystal-less operation enabled in device mode via software library (TN00063) |
| VDDA / VSSA | Analog Power Supply / Ground | Independent 1.8–3.6 V analog domain supply; requires separate filtering from digital VDD/VSS |
Key Features
| Feature | Design Value |
|---|---|
| PRINCE Flash Encryption | Hardware-accelerated AES-128 real-time encryption/decryption of flash reads/writes-enables secure OTA updates without software overhead |
| CASPER Crypto Engine | Dedicated hardware for ECC scalar multiplication (P-256/P-384), SHA-256, and AES-256-reduces crypto latency by >10× vs. software-only implementation |
| Secure Boot with RoT | Four revocable Root-of-Trust keys stored as SHA-256 hashes in protected flash; anti-rollback enforced via x.509 serial number revocation |
| Flexcomm Serial Peripherals | Nine configurable serial interfaces with shared FIFO and fractional baud-rate generator-eliminates need for external UART/SPI/I²C bridges |
| Low-Power Operation | Deep power-down mode with RAM retention; wake-up via RTC (1 ms resolution), Micro-Tick Timer (FRO 1 MHz), or GPIO interrupt-typical current < 1.5 µA |
| ADC Simultaneous Sampling | 16-bit ADC supports concurrent sampling on paired differential channels (e.g., CH1A/CH1B)-critical for motor current sensing and phase-resolved measurements |
Applications
| Industrial PLC I/O Module | Secure Edge Gateway |
|---|---|
Use Scenario: Programmable logic controller module collecting analog sensor data and controlling relay outputs in factory automation. IC Role / Device Role / Timing Role: Main application processor executing real-time control loop, ADC sampling at 1 MS/s, and secure firmware update handling. Use Value: PRINCE encryption protects proprietary control algorithms in flash; CASPER accelerates TLS handshake for encrypted MQTT communication to cloud platform. |
Use Scenario: Field-deployed gateway aggregating data from legacy Modbus RTU devices and forwarding to IIoT platform via TLS-secured HTTP/HTTPS. IC Role / Device Role / Timing Role: Secure host processor managing multiple serial protocols, USB host for configuration dongle, and high-speed USB for firmware updates. Use Value: Dual USB (FS + HS) enables simultaneous device-mode configuration and host-mode bulk data transfer; PUF-derived keys prevent cloning of gateway identity. |
| Smart Energy Meter | Medical Sensor Hub |
Use Scenario: Revenue-grade electricity meter performing harmonic analysis, tamper detection, and secure remote firmware updates. IC Role / Device Role / Timing Role: Primary MCU running metrology algorithm, RTC for time-stamped billing, and secure boot validation before each boot. Use Value: 16-bit ADC with simultaneous dual-channel sampling captures voltage/current waveforms for IEEE 1459-compliant power calculation; SHA2-AES engine signs firmware images. |
Use Scenario: Portable patient monitor hub collecting ECG, temperature, and SpO₂ data from multiple sensors and transmitting via BLE or USB to clinical tablet. IC Role / Device Role / Timing Role: Central data concentrator with integrated ADC, comparator for signal integrity checks, and secure storage of calibration coefficients. Use Value: Integrated temperature sensor calibrates ADC offset drift; secure GPIO isolates critical alarm lines from untrusted peripherals; TRNG seeds cryptographic keys for HIPAA-compliant data encryption. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar secure Arm Cortex-M33 microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC55S16JBD64 | Same HTQFP64 package; 256 KB flash, 144 KB SRAM, no PRINCE or PUF; CASPER present | Lacks flash encryption and silicon PUF-unsuitable for applications requiring certified secure boot or key attestation | Select when cost sensitivity outweighs need for PRINCE/PUF and flash size ≤256 KB suffices |
| RA6M5GFP64FB | Renesas RA6M5, 200 MHz Cortex-M33, 1 MB flash, 384 KB SRAM, no CASPER, TrustZone only, no PRINCE | Higher performance and memory but lacks hardware crypto acceleration-requires software TLS stack with higher CPU load | Choose for high-throughput data logging where crypto offload is not required and larger memory footprint is acceptable |
Compared with LPC55S28JBD64E, LPC55S16JBD64 reduces BOM cost by omitting PRINCE/PUF but sacrifices certified secure boot; RA6M5GFP64FB offers more memory and speed but increases firmware development effort for crypto due to absence of CASPER and PRINCE.
Availability
LPC55S28JBD64E is available at Aetrix Electronics and suitable for industrial PLC modules, secure edge gateways, smart energy meters, and medical sensor hubs requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for LPC55S28JBD64E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT markets, with core expertise in Arm-based MCUs and embedded security.
The LPC55S2x series targets secure, low-power edge intelligence applications-designed to deliver hardware-rooted trust, real-time performance, and flexible connectivity in compact packages for industrial and medical end equipment.
FAQ
What is the maximum operating frequency of the LPC55S28JBD64E?
The LPC55S28JBD64E operates at up to 150 MHz using its Arm Cortex-M33 core. This frequency is achievable with PLL0 or PLL1 clock sources derived from internal FRO (12 MHz or 1 MHz), external crystal (16–32 MHz), or 32.768 kHz RTC oscillator. The FRO is factory-trimmed to ±1% accuracy across 0 °C to 85 °C for date codes 2041 and later.
Does the LPC55S28JBD64E support crystal-less USB full-speed device operation?
Yes, the LPC55S28JBD64E supports crystal-less USB full-speed device mode using its internal 48 MHz clock derived from the FRO. This capability is implemented in hardware and enabled via software library example TN00063-eliminating the need for an external 48 MHz crystal and reducing BOM cost and board space.
How many GPIO pins does the LPC55S28JBD64E provide in the HTQFP64 package?
The LPC55S28JBD64E in HTQFP64 package provides 36 general-purpose I/O pins. These include 8 pins configurable as pin interrupts (PINT) with rising/falling/both-edge detection, and 2 GPIO group interrupts (GINT) supporting logical AND/OR combinations of input states for efficient event aggregation.
What security features distinguish the LPC55S28JBD64E from standard Cortex-M33 MCUs?
The LPC55S28JBD64E integrates hardware security features beyond baseline TrustZone: PRINCE for real-time flash encryption, CASPER for ECC/SHA/AES acceleration, PUF for silicon-fingerprint-based key generation (64–4096 bits), TRNG, secure GPIO, and debug authentication with RSA-2048/4096-enabling NIST SP 800-193 compliant secure boot and firmware update.
Is the LPC55S28JBD64E pin-compatible with other members of the LPC55S2x family in HTQFP64?
Yes, the LPC55S28JBD64E is pin-compatible with LPC55S26JBD64 and LPC552x variants in the HTQFP64 package. All share identical pinout, electrical characteristics, and peripheral mapping-allowing drop-in replacement where flash size (512 KB vs. 256 KB) and security features (PRINCE/PUF presence) meet design requirements.
LPC55S28JBD64E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 64-TQFP Exposed Pad
- Series:
- LPC55S2x
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit Single-Core
- Speed:
- 150MHz
- Connectivity:
- Flexcomm, I2C, MMC/SD/SDIO, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, PWM, RNG, WDT
- Number of I/O:
- 36
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 10x16b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC55S28JBD64E FAQ
1.How can I place an order for LPC55S28JBD64E through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC55S28JBD64E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC55S28JBD64E reliable?
The price and inventory of LPC55S28JBD64E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC55S28JBD64E is usually 5 days.
3.What payment methods are accepted for LPC55S28JBD64E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC55S28JBD64E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC55S28JBD64E?
LPC55S28JBD64E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC55S28JBD64E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC55S28JBD64E?
For technical support, including LPC55S28JBD64E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC55S28JBD64E requirements.
6.How does Aetrix verify that LPC55S28JBD64E is sourced from the original manufacturer or authorized distributors?
All LPC55S28JBD64E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC55S28JBD64E meets industry standards.
7.What is the process for return or replacement of LPC55S28JBD64E?
All LPC55S28JBD64E units undergo pre-shipment inspection (PSI). If there is an issue with LPC55S28JBD64E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC55S28JBD64E part is unused and in its original packaging.
Return procedure for LPC55S28JBD64E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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