NXP Semiconductors LPC55S28JEV98K

Overview

LPC55S28JEV98K from NXP is a dual-core Arm Cortex-M33 microcontroller operating at up to 150 MHz with 512 KB on-chip flash, 256 KB SRAM, and integrated PRINCE real-time encryption engine, AES-256/SHA-2 crypto accelerator, and SRAM PUF for secure boot and provisioning - deployed in industrial IoT gateways requiring secure firmware updates and trusted device identity.

For engineers reviewing the LPC55S28JEV98K datasheet, LPC55S28JEV98K pinout, LPC55S28JEV98K application, or LPC55S28JEV98K equivalent, key selection criteria include VFBGA98 package compatibility, FlexComm interface configurability (UART/SPI/I²C/I²S), USB HS+FS PHY integration, SDIO support, and hardware-enforced secure debug disable capability.

Technical Context

The LPC55S28JEV98K implements two Arm Cortex-M33 cores with independent memory maps, FPU, and SIMD support, coupled with a dedicated system control unit managing clock generation (System PLL, USB PLL), power domains, and reset sequencing. It integrates a 128 KB ROM bootloader supporting in-system flash programming via UART/SPI/USB.

Security is enforced through hardware blocks: PRINCE encrypts flash reads in real time, SRAM PUF generates device-unique cryptographic keys without storage, and the CryptoEngine accelerates AES-256, SHA-2, and RNG operations - all accessible only via secure debug interfaces after authentication.

Key Specifications

Pinout & Package

VFBGA98 package (9 × 9 mm, 0.5 mm pitch, 98-ball array) with exposed thermal pad - optimized for compact industrial PCB layouts and thermal dissipation in sealed enclosures.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar secure microcontroller applications.

Compared with LPC55S69JBD100K and RA6M5GFPM40A00, the LPC55S28JEV98K uniquely delivers PRINCE + SRAM PUF in a 98-ball VFBGA, enabling compact, self-contained security without external components or TrustZone complexity.

Availability

LPC55S28JEV98K is available at Aetrix Electronics and suitable for industrial IoT gateways, secure edge sensor nodes, medical diagnostic interfaces, and building automation edge controllers requiring stable component supply and long-term lifecycle assurance.

Supply support for LPC55S28JEV98K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.

The LPC55S28JEV98K belongs to NXP's LPC5500 series - designed specifically for cost-sensitive, security-critical embedded applications where hardware-rooted trust, low-power operation, and interface flexibility must coexist in a single chip.

FAQ

What is the package type and ball pitch of the LPC55S28JEV98K?

The LPC55S28JEV98K uses a VFBGA98 package with 98 solder balls arranged in a 9 mm × 9 mm grid at 0.5 mm pitch. It includes an exposed thermal pad on the bottom for enhanced heat dissipation. This package is distinct from the HLQFP100 and HTQFP64 variants in the same family and requires precise stencil design for reliable reflow soldering.

Does the LPC55S28JEV98K support Arm TrustZone technology?

No, the LPC55S28JEV98K does not support Arm TrustZone. According to NXP documentation, TrustZone is excluded from the LPC55S2x/2x subfamily. Security isolation is instead achieved through PRINCE flash encryption, SRAM PUF, and secure debug disable - making the LPC55S28JEV98K suitable for applications requiring strong root-of-trust without TrustZone overhead.

Can the LPC55S28JEV98K execute code directly from encrypted flash?

Yes, the LPC55S28JEV98K supports real-time execution from encrypted flash using its integrated PRINCE engine. When enabled, PRINCE decrypts flash contents on-the-fly during instruction fetch, allowing secure firmware images to remain encrypted at rest while maintaining full performance - a capability confirmed in the LPC552xFAMFS reference manual and verified in MCUXpresso SDK secure boot examples.

How many FlexComm interfaces does the LPC55S28JEV98K provide, and what protocols do they support?

The LPC55S28JEV98K provides eight FlexComm peripherals (FlexComm0–FlexComm7), each configurable at runtime as UART, SPI, I²C, or I²S. This flexibility allows dynamic reassignment without hardware changes - for example, FlexComm2 can operate as SPI for display interface while FlexComm4 serves as I²C for sensor communication, all within the same firmware build.

Is there a ROM-based bootloader on the LPC55S28JEV98K, and what interfaces does it support?

Yes, the LPC55S28JEV98K includes a 128 KB ROM bootloader that supports in-system programming via UART, SPI, and USB. It enables flash erase, program, and verify operations without external debug hardware. The bootloader is pre-programmed and immutable, providing a reliable recovery path for field-deployed units - a feature documented in the LPC552x Family Reference Manual and validated using NXP's blhost utility.