NXP Semiconductors LPC55S28JEV98Y
- Part No.:
- LPC55S28JEV98Y
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 98-VFBGA
- Datasheet:
-
LPC55S28JEV98Y.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 98VFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:2,000
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Product details
Overview
LPC55S28JEV98Y from NXP Semiconductors is a 32-bit Arm Cortex-M33 microcontroller with CASPER crypto co-processor, 512 KB flash, 256 KB SRAM, PRINCE real-time flash encryption, and dual-mode USB (FS + HS), deployed in secure IoT edge nodes requiring cryptographic acceleration and low-power operation.
For engineers reviewing the LPC55S28JEV98Y datasheet, LPC55S28JEV98Y pinout, LPC55S28JEV98Y application, or LPC55S28JEV98Y equivalent, key selection criteria include its VFBGA98 package, 150 MHz CPU frequency, PUF-based key generation, SHA2/AES hardware acceleration, and support for secure boot with RSA-2048/4096 and x.509 certificate validation.
Technical Context
The LPC55S28JEV98Y implements an Arm Cortex-M33 core (r0p3) with MPU, FPU, DSP, and ETM, running at up to 150 MHz using PLL0/PLL1 clock sources derived from internal FRO (12 MHz/1 MHz), external crystal (16–32 MHz), or RTC oscillator (32.768 kHz). Its security architecture integrates PRINCE for on-the-fly encrypted flash access, PUF for silicon-unique 64–4096-bit key derivation, and dedicated HASH-AES/SHA2 engines with DMA support.
Peripheral flexibility is enabled by nine Flexcomm interfaces (FC0–FC8), each configurable as USART/SPI/I2C/I2S with FIFO and fractional baud-rate generation; FC8 is dedicated high-speed SPI. The SCTimer/PWM supports 16 capture/match registers and 32 states, while the 16-bit ADC achieves 1.0 Msamples/sec with simultaneous differential conversions and integrated temperature sensing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 (r0p3) with MPU, FPU, DSP, ETM - enables TrustZone-based secure partitioning and deterministic real-time execution. |
| Max Clock Frequency | 150 MHz - achieved via PLL0/PLL1 using internal FRO or external crystal, supporting high-throughput crypto and signal processing. |
| Memory | 512 KB on-chip flash (512-byte page erase/write) + 256 KB SRAM (32 KB code bus, 208 KB system bus, 16 KB USB SRAM) - enables large firmware images and dual-bank OTA updates. |
| Security Features | PRINCE flash encryption, PUF key generation, SHA2/AES-256, RSA-2048/4096, secure boot with x.509 RoT revocation - meets TBSA compliance for certified secure boot chains. |
| Analog Peripherals | 16-bit ADC (1.0 Msamples/sec, 5 differential/10 single-ended channels), comparator, temperature sensor - supports precision sensor fusion without external ADC. |
| Serial Interfaces | 9 Flexcomm peripherals (configurable USART/SPI/I2C/I2S), USB 2.0 FS+HS host/device with crystal-less FS mode, SDIO (SD2.0/SDR25) - enables multi-protocol connectivity in space-constrained designs. |
| Package | VFBGA98 (7 mm × 7 mm, 0.5 mm pitch, SOT1982-1) - provides high I/O density and thermal performance for compact industrial and wearable applications. |
Pinout & Package
VFBGA98 package (SOT1982-1), 7 mm × 7 mm body, 0.5 mm ball pitch, 98 I/O balls. Pin functions are software-configurable via IOCON registers; default reset state includes pull-up on PIO0_5 and PIO0_12, pull-down on PIO0_2 and PIO0_11, and open-drain on PIO0_13/PIO0_14.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PIO0_0 / ACMP0_A | GPIO / Analog Comparator Input A | Dual-role pin supporting digital I/O or comparator input when analog mode enabled - enables compact sensor threshold detection. |
| PIO0_5 | Boot Source Selector / TDI | State at reset determines boot source (flash/ISP); also serves as JTAG TDI - critical for production programming and debug access. |
| PIO0_11 / ADC0_9 | GPIO / ADC Channel 1B (differential negative) | Configurable as GPIO or ADC input; pairs with PIO0_10 for differential sampling - improves noise immunity in analog front-ends. |
| SWCLK / PIO0_12 | Serial Wire Debug Clock | Primary debug interface clock; default function after boot - enables non-intrusive trace and breakpoint debugging. |
| FC3_SCK / PIO0_2 | Flexcomm 3 Clock | Shared with TRST in boundary scan mode - supports flexible peripheral routing while maintaining JTAG testability. |
Key Features
| Feature | Design Value |
|---|---|
| CASPER Crypto Co-processor | Hardware acceleration for ECC and FFT operations - reduces CPU load and latency for TLS handshake and secure firmware updates. |
| PRINCE Flash Encryption | Real-time AES-128 encryption/decryption of flash reads/writes - protects IP and enables secure field updates without exposing decrypted code. |
| Secure Boot with x.509 RoT | Support for four revocable Root of Trust keys stored as SHA-256 hashes in protected flash - prevents rollback attacks and enforces chain-of-trust integrity. |
| Programmable Logic Unit (PLU) | Configurable combinatorial/sequential logic with state machine support - replaces discrete glue logic and enables custom peripheral synchronization. |
| Micro-Tick Timer + RTC Wake-up | Independent 1 MHz watchdog oscillator timer and 32.768 kHz RTC - allows precise sub-second wake-up from deep-sleep with minimal power overhead. |
Applications
| Industrial Sensor Hub | Secure Wearable Gateway |
|---|---|
Use Scenario: Multi-sensor data aggregation (temperature, humidity, motion) with local preprocessing and encrypted transmission to cloud. IC Role / Device Role / Timing Role: Main application processor executing RTOS, managing ADC/SPI/I2C sensors, running TLS stack, and controlling USB/SDIO uplink. Use Value: CASPER accelerates ECC-based TLS handshakes; PRINCE secures firmware updates; 256 KB SRAM buffers sensor streams before encryption. |
Use Scenario: Health-monitoring wearable collecting ECG/PPG data, enforcing HIPAA-compliant local storage and authenticated Bluetooth LE pairing. IC Role / Device Role / Timing Role: Trusted execution environment host with PUF-derived keys, secure GPIO isolation, and tamper-resistant RTC timestamping. Use Value: PUF generates unique device keys without storage; SHA2/AES engine signs sensor logs; secure boot ensures only signed firmware executes. |
| Smart Home Edge Controller | Automotive Body Control Module (BCM) Subsystem |
Use Scenario: Local voice assistant hub coordinating Zigbee/Z-Wave devices, performing on-device keyword spotting, and enforcing local policy decisions. IC Role / Device Role / Timing Role: Real-time audio preprocessor (via MRT timers and PLU), secure communication gateway (USB/SDIO), and trusted policy enforcement node. Use Value: SCTimer/PWM synchronizes audio sampling; Flexcomm interfaces manage multiple radio stacks; secure GPIO isolates critical control outputs. |
Use Scenario: Low-voltage subsystem managing door locks, lighting, and diagnostics in 12 V automotive environments with ASIL-B functional safety requirements. IC Role / Device Role / Timing Role: Safety-monitored controller with windowed watchdog (WWDT), brown-out detection (BOD), and fail-safe GPIO configuration. Use Value: WWDT with FRO 1 MHz clock ensures deterministic reset on timing faults; BOD interrupts prevent erratic behavior during battery sag; GPIO pin interrupts enable fast lock/unlock response. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC55S26JEV98 | 256 KB flash, 144 KB SRAM, same CASPER/PRINCE/PUF/security features and VFBGA98 package | Suitable for cost-sensitive designs with smaller firmware footprints and reduced RAM requirements | Select when application firmware fits within 256 KB flash and does not require full 256 KB SRAM allocation. |
| LPC5528JEV98 | No CASPER, no PRINCE, no PUF, no secure boot - identical package, clock, and peripheral set otherwise | Targeted at non-security-critical consumer applications where crypto acceleration and flash encryption are unnecessary | Choose only if security features are explicitly excluded from system requirements and BOM cost reduction is prioritized over future-proofing. |
Compared with LPC55S26JEV98, the LPC55S28JEV98Y offers double flash and 112 KB more SRAM for complex OTA stacks and ML inference buffers; versus LPC5528JEV98, it adds hardware-enforced security primitives essential for certified IoT deployments - making it the only option meeting TBSA and PSA Certified Level 2 requirements.
Availability
LPC55S28JEV98Y is available at Aetrix Electronics and suitable for industrial sensor hubs, secure wearables, smart home edge controllers, and automotive BCM subsystems requiring stable component supply across long-life production cycles.
Supply support for LPC55S28JEV98Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in Arm-based microcontrollers and hardware security.
The LPC55S2x series was designed to deliver scalable, certified security (TBSA, PSA Level 2) and real-time performance in resource-constrained edge devices - targeting applications where firmware integrity, cryptographic agility, and low-power operation are mandatory.
FAQ
What is the maximum operating frequency of the LPC55S28JEV98Y?
The LPC55S28JEV98Y operates at a maximum CPU frequency of 150 MHz, achieved using PLL0 or PLL1 clock sources derived from the internal 12 MHz FRO, external crystal (16–32 MHz), or 32.768 kHz RTC oscillator. This frequency is sustained across the full industrial temperature range (−40 °C to +105 °C) and supported by the Arm Cortex-M33 core's FPU and DSP extensions. The LPC55S28JEV98Y maintains timing compliance under all specified voltage (1.8–3.6 V) and thermal conditions.
Does the LPC55S28JEV98Y support secure boot with public-key cryptography?
Yes, the LPC55S28JEV98Y supports secure boot using RSASSA-PKCS1-v1_5 signatures of SHA256 digests, with RSA-2048 and RSA-4096 public keys validated against x.509 certificates. It stores up to four revocable Root of Trust keys as SHA-256 hashes in protected flash and enforces anti-rollback via image key certificate revocation. This implementation complies with TBSA and enables PSA Certified Level 2 deployment. The LPC55S28JEV98Y requires no external secure element for root key storage.
What package type and pin count does the LPC55S28JEV98Y use?
The LPC55S28JEV98Y uses a VFBGA98 package (SOT1982-1): thin fine-pitch ball grid array with 98 solder balls, 7 mm × 7 mm body size, and 0.5 mm pitch. This package supports high I/O density and thermal efficiency in compact PCB layouts. Pin functions-including GPIO, Flexcomm, ADC, USB, and debug signals-are software-configurable via IOCON registers, with documented reset states for critical pins like PIO0_5 (boot select) and PIO0_11 (ADC0_9).
How does the PRINCE module function in the LPC55S28JEV98Y?
The PRINCE module in the LPC55S28JEV98Y performs real-time AES-128 encryption of data written to on-chip flash and decryption of encrypted data read from flash. It operates transparently to software, enabling asset protection (e.g., application code obfuscation) and secure firmware updates without runtime CPU overhead. The LPC55S28JEV98Y supports booting directly from PRINCE-encrypted flash regions, and key management is handled internally-no software exposure of encryption keys occurs during operation.
Which analog peripherals are integrated into the LPC55S28JEV98Y?
The LPC55S28JEV98Y integrates a 16-bit ADC with 1.0 Msamples/sec sampling rate, supporting five differential or ten single-ended input channels; an analog comparator with five inputs and selectable internal/external reference; and an integrated temperature sensor connected to the ADC. These peripherals share DMA channels and support simultaneous conversions on differential pairs. The LPC55S28JEV98Y does not require external signal conditioning for basic environmental monitoring or motor current sensing in industrial applications.
LPC55S28JEV98Y Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 98-VFBGA
- Series:
- LPC55S2x
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit Single-Core
- Speed:
- 150MHz
- Connectivity:
- Flexcomm, I2C, MMC/SD/SDIO, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, PWM, RNG, WDT
- Number of I/O:
- 64
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 10x16b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC55S28JEV98Y FAQ
1.How can I place an order for LPC55S28JEV98Y through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC55S28JEV98Y on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC55S28JEV98Y reliable?
The price and inventory of LPC55S28JEV98Y are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC55S28JEV98Y is usually 5 days.
3.What payment methods are accepted for LPC55S28JEV98Y?
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LPC55S28JEV98Y orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC55S28JEV98Y order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC55S28JEV98Y?
For technical support, including LPC55S28JEV98Y datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC55S28JEV98Y requirements.
6.How does Aetrix verify that LPC55S28JEV98Y is sourced from the original manufacturer or authorized distributors?
All LPC55S28JEV98Y products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC55S28JEV98Y meets industry standards.
7.What is the process for return or replacement of LPC55S28JEV98Y?
All LPC55S28JEV98Y units undergo pre-shipment inspection (PSI). If there is an issue with LPC55S28JEV98Y, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC55S28JEV98Y part is unused and in its original packaging.
Return procedure for LPC55S28JEV98Y:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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