NXP Semiconductors LPC55S36JBD100E

Overview

LPC55S36JBD100E from NXP Semiconductors is a 32-bit ARM Cortex-M33 microcontroller with TrustZone security, 256 KB flash, 128 KB SRAM, PRINCE on-the-fly flash encryption, PKC hardware accelerator, and CAN FD interface. It operates up to 150 MHz and supports crystal-less USB Full-Speed device mode. Used in secure industrial edge nodes requiring authenticated firmware updates and real-time motor control.

For engineers reviewing the LPC55S36JBD100E datasheet, LPC55S36JBD100E pinout, LPC55S36JBD100E application, or LPC55S36JBD100E equivalent, key selection considerations include TrustZone-enforced memory isolation, dual FlexPWM for dual 3-phase motor control, PRINCE-encrypted XIP from FlexSPI, PUF-derived AES keys, and tamper-detect-capable secure boot per TBSA.

Technical Context

The LPC55S36JBD100E integrates an ARM Cortex-M33 core with TrustZone, FPU, and MPU, enabling hardware-isolated secure and non-secure execution environments. Its Edge Lock Subsystem (ELS) manages cryptographic operations including ECDSA P-256/P-384 signature verification and SB3.1 firmware update validation.

Security is enforced via PRINCE (three internal flash regions), PKC (four 4 KB SRAM banks), PUF (64–4096-bit key generation), and DICE-compliant Device Identifier Composition Engine. The chip supports dual-image boot with anti-rollback using monotonic Secure_FW_Version counters and revocable Root of Trust keys stored in protected flash.

Key Specifications

Pinout & Package

HLQFP100 package: 100-pin plastic low-profile quad flat package, 0.5 mm pitch, 14 mm × 14 mm body size, exposed thermal pad. Pin functions are software-configurable via IOCON registers; default reset state disables pull-ups/pull-downs except on debug and boot pins (PIO0_0–PIO0_5, PIO0_9, PIO0_13–PIO0_14).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar secure microcontroller applications.

Compared with LPC55S28JBD100E and RA6M5GFP100AA00, the LPC55S36JBD100E uniquely delivers PRINCE-encrypted XIP, PKC-accelerated ECDSA P-384, and DICE-compliant device identity - making it the only option for TBSA-aligned secure boot with anti-rollback enforcement in HLQFP100 form factor.

Availability

LPC55S36JBD100E is available at Aetrix Electronics and suitable for industrial motor control, secure edge gateways, medical diagnostics, automotive body electronics, and tamper-evident IoT endpoints requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for LPC55S36JBD100E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in ARM-based microcontrollers and cryptographic subsystem design.

The LPC55S3x product line was designed to deliver certified secure boot, hardware-accelerated cryptography, and real-time control capabilities in a single chip for resource-constrained edge devices requiring TBSA compliance and extended-temperature operation.

FAQ

What is the maximum operating frequency of the LPC55S36JBD100E?

The LPC55S36JBD100E operates at a maximum CPU frequency of 150 MHz using its ARM Cortex-M33 core. This speed is achievable with PLL0 or PLL1 clock sources derived from the internal 12 MHz FRO, external crystal (16–32 MHz), or 32.768 kHz RTC oscillator. The FRO is factory-trimmed to ±1% accuracy across 0 °C to 85 °C, ensuring stable timing for real-time control loops in the LPC55S36JBD100E.

Does the LPC55S36JBD100E support crystal-less USB Full-Speed device operation?

Yes, the LPC55S36JBD100E supports crystal-less USB Full-Speed device mode using its internal 48 MHz FRO and software library AN13527. This eliminates the need for an external 12 MHz crystal, reducing BOM cost and board area. The LPC55S36JBD100E achieves ±0.25% frequency tolerance required for USB compliance through FRO calibration and runtime trimming - confirmed in NXP's official application note.

How many secure boot root-of-trust keys does the LPC55S36JBD100E support?

The LPC55S36JBD100E supports up to four revocable Root of Trust (RoT) or Certificate Authority public keys, stored as SHA-2 hash digests in the Protected Flash Region (PFR). Each key can be revoked individually using the IMAGE_KEY_REVOKE 32-bit monotonic counter in CFPA, allowing up to 4,294,967,295 revocations. This mechanism is enforced during every boot and firmware update in the LPC55S36JBD100E.

What analog peripherals are integrated into the LPC55S36JBD100E?

The LPC55S36JBD100E integrates four 16-bit ADCs (2.0 Msamples/sec), three 12-bit DACs (1.0 Msamples/sec), three operational amplifiers (OpAmps), four comparators (including one in the always-on domain), and two temperature sensors. ADCs support four simultaneous conversions across independent sequences, and OpAmp0 output is routed to a pin while OpAmp1/2 outputs remain internal - all confirmed in Table 2 of the LPC55S3x datasheet for the LPC55S36JBD100E.

Is the LPC55S36JBD100E pin-compatible with other LPC55S3x variants in HLQFP100?

Yes, the LPC55S36JBD100E shares identical pinout and package (HLQFP100, SOT1570-5) with other LPC55S3x family members in the same package, including LPC55S36JBD100K and LPC55S36JBD100MP. All HLQFP100 variants use the same 100-pin mapping, IOCON register structure, and reset configuration - enabling direct PCB reuse across ordering options and compatible flash/SRAM configurations within the LPC55S3x series.