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NXP Semiconductors LPC55S36JBD100K
- Part No.:
- LPC55S36JBD100K
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
LPC55S36JBD100K.pdf
- Description:
- IC MCU 32BIT 256KB FLSH 100HLQFP
- Quantity:
- Payment:
- Shipping:
Inventory:430
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Product details
Overview
LPC55S36JBD100K from NXP Semiconductors is a 32-bit ARM Cortex-M33 microcontroller with TrustZone security, 256 KB flash, 128 KB SRAM, PRINCE real-time flash encryption, PKC cryptographic accelerator, and CAN FD interface - deployed in secure industrial gateways requiring authenticated firmware updates and tamper-resistant edge control.
For engineers reviewing the LPC55S36JBD100K datasheet, LPC55S36JBD100K pinout, LPC55S36JBD100K application, or LPC55S36JBD100K equivalent, this page delivers verified specifications, package mapping to HLQFP100, security architecture context, and validated alternative options for secure MCU selection.
Technical Context
The LPC55S36JBD100K implements ARM TrustZone® at silicon level to isolate secure and non-secure execution states, with dedicated Edge Lock Subsystem (ELS) managing root-of-trust boot and runtime attestation. Its PRINCE module performs inline AES-128 encryption/decryption of flash reads and writes, while PKC accelerates ECC secp256r1/secp384r1 and RSA operations using four 4 KB AHB-accessible SRAM banks.
It integrates dual DMA controllers (52+16 channels), FlexSPI with 8 KB cache and dynamic decryption for XIP from Octal/QuadSPI, and two FlexPWM subsystems supporting dual 3-phase motor control. The device supports crystal-less USB FS device operation via software library AN13527 and includes PUF-based key generation, SHA-256/384, AES-GCM, and DICE-compliant Device Identifier Composition Engine.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M33 @ up to 150 MHz with FPU, MPU, and TrustZone® - enables deterministic real-time control with hardware-enforced memory isolation. |
| Memory | 256 KB on-chip flash (246 KB usable), 128 KB SRAM (16 KB Code Bus + 112 KB System Bus) - supports dual-image boot and secure firmware updates via SB3.1 format. |
| Security | PRINCE flash encryption, PKC accelerator, PUF, AES-256/GCM, SHA-256/384, ECDSA P-256/P-384, DICE v2.0 - meets TBSA requirements for secure boot and runtime integrity. |
| Connectivity | CAN FD with dedicated DMA, USB 2.0 Full-Speed host/device (crystal-less mode supported), I3C, 8x Flexcomm interfaces (configurable as USART/SPI/I2C/I2S) - enables mixed-protocol industrial edge node design. |
| Analog | Four 16-bit ADCs (2.0 Msps), three 12-bit DACs (1.0 Msps), four comparators, three OpAmps, integrated temperature sensor - supports closed-loop analog sensing and actuation without external signal chain. |
| Timers & PWM | Five 32-bit general-purpose timers, SCTimer/PWM (16 match/capture registers), two FlexPWM (24 outputs), MRT, RTC, WWDT - delivers precise motor control, audio timing, and low-power wake-up scheduling. |
| Package | HLQFP100 (14 × 14 × 0.5 mm, 0.5 mm pitch) - provides 66 GPIOs, full peripheral pinout access, and thermal performance suitable for industrial ambient (−40 °C to +105 °C). |
Pinout & Package
HLQFP100 plastic low-profile quad flat package with 100 leads; body size 14 × 14 × 0.5 mm, 0.5 mm pitch; lead finish matte tin; RoHS compliant; thermal pad exposed on underside for enhanced heat dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PIO0_0 / ACMP0_A | GPIO / Analog comparator input A | Dual-function pin supporting digital I/O or differential ADC input when analog mode enabled - used for secure sensor interface or wake-up trigger. |
| PIO0_5 / TDI | JTAG test data input / CAN0_TD | Boot source selector (with PIO0_7); default internal pull-up enables ISP entry - critical for recovery programming and debug authentication flow. |
| PIO0_13 / SWDIO | Serial Wire Debug I/O | True open-drain configuration allows shared SWD bus with other devices; required for secure debug authentication using ECDSA P-256 keys. |
| FLEXSPI0_DATA3 | FlexSPI data line D3 | Part of high-speed octal/quad SPI interface with 8 KB cache and dynamic decryption - enables execute-in-place from encrypted external flash. |
| USB_DP / USB_DM | USB 2.0 Full-Speed differential pair | On-chip PHY supports crystal-less operation in device mode - eliminates external 12 MHz crystal, reducing BOM cost and board space. |
Key Features
| Feature | Design Value |
|---|---|
| Edge Lock Subsystem (ELS) | Hardware-managed secure boot, attestation, and lifecycle state control - enforces anti-rollback via monotonic Secure_FW_Version counter and image key revocation. |
| PRINCE Inline Encryption | Real-time AES-128 encryption/decryption of flash reads/writes across up to three internal regions - protects IP without software overhead or latency penalty. |
| PowerQuad DSP Accelerator | Fixed/floating-point math engine with four 4 KB SRAM banks accessible by CPU/DMA - offloads FFT, filtering, and motor control algorithms from Cortex-M33 core. |
| Secure GPIO & Tamper Detection | Four dedicated tamper inputs with RTC-filtered glitch rejection and timestamped queue - detects physical intrusion attempts and triggers secure erase of sensitive keys. |
| Digital Microphone Interface (DMIC) | Two-channel PDM input with decimators and Voice Activation Detect - enables always-on voice wake-up without CPU involvement, reducing active power in low-power modes. |
Applications
| Industrial Gateway Security | Secure Motor Control Edge Node |
|---|---|
|
Use Scenario: Field-deployed gateway authenticating firmware updates over cellular or Ethernet before installation. IC Role / Device Role / Timing Role: Root-of-trust anchor executing ECDSA-signed SB3.1 images, verifying SHA-256 digests, and enforcing anti-rollback using Secure_FW_Version. Use Value: Prevents unauthorized code execution via hardware-secured boot ROM and PRINCE-encrypted flash storage - eliminates need for external secure element. |
Use Scenario: Compact servo drive controlling dual BLDC motors in factory automation equipment. IC Role / Device Role / Timing Role: Real-time controller running FOC algorithms via PowerQuad, generating synchronized PWM waveforms using two FlexPWM modules (24 outputs). Use Value: Achieves <1 µs PWM edge jitter and sub-microsecond interrupt latency - enables precise torque ripple reduction and EMI optimization. |
| Smart Building Sensor Hub | Medical Diagnostic Edge Analyzer |
|
Use Scenario: Battery-powered environmental monitor aggregating CO₂, humidity, and acoustic data for cloud upload. IC Role / Device Role / Timing Role: Low-power coordinator using RTC wake-up, DMIC voice activation, and 16-bit ADC sampling at 2.0 Msps for transient event capture. Use Value: Enables 5-year battery life via deep-sleep with RAM retention and micro-tick timer wake-up - no external RTC or PMIC required. |
Use Scenario: Portable ultrasound front-end digitizing analog transducer signals with calibrated gain and offset correction. IC Role / Device Role / Timing Role: Precision analog subsystem using three 12-bit DACs (1.0 Msps), four comparators, and OpAmp0 output routed to pin for analog signal conditioning. Use Value: Delivers <±0.5 LSB INL and 72 dB SNR - meets Class II medical device accuracy requirements without external calibration components. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar secure microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC55S28JBD100K | Same package and core, but 128 KB flash, 64 KB SRAM, no PRINCE, no PKC, no CAN FD - lacks inline flash encryption and public-key acceleration. | Suitable for cost-sensitive secure boot applications without field-upgradable encrypted assets or asymmetric crypto workload. | Select when firmware size ≤128 KB and cryptographic operations are limited to AES/SHA only - reduces bill-of-materials cost by ~18%. |
| RA6M5GFPMXXFA | Renesas RA6M5 with Cortex-M33, 1 MB flash, 448 KB SRAM, TrustZone, but no PRINCE, no PKC, no PUF, no DMIC - uses external secure element for key storage. | Targeted at high-memory HMI and connectivity hubs where external QSPI flash and Ethernet MAC dominate resource use. | Choose when >512 KB flash and Ethernet/USB HS are required - accepts trade-off of external secure element integration effort. |
Compared with LPC55S36JBD100K, LPC55S28JBD100K reduces security depth and memory capacity for lower-cost deployments, while RA6M5GFPMXXFA expands memory and connectivity at the expense of integrated cryptographic acceleration and tamper resilience - making LPC55S36JBD100K optimal for compact, self-contained secure edge nodes.
Availability
LPC55S36JBD100K is available at Aetrix Electronics and suitable for industrial gateways, motor control drives, smart building sensor hubs, and portable medical analyzers requiring stable component supply across extended product lifecycles.
Supply support for LPC55S36JBD100K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with R&D centers in Eindhoven, Austin, and Singapore.
The LPC55S3x product line delivers scalable, TrustZone-enabled MCUs designed for secure edge intelligence - integrating hardware-rooted security, real-time control, and low-power operation into single-chip solutions for industrial and medical applications.
FAQ
What is the maximum operating frequency of the LPC55S36JBD100K?
The LPC55S36JBD100K operates at a maximum CPU frequency of 150 MHz using its ARM Cortex-M33 core. This speed is achievable with PLL0 or PLL1 clock sources derived from the internal 96 MHz FRO, external crystal (16–32 MHz), or 32.768 kHz RTC oscillator. The device maintains timing compliance across its full −40 °C to +105 °C industrial temperature range, with voltage regulation via integrated DC-DC converter or LDO.
Does the LPC55S36JBD100K support crystal-less USB Full-Speed device operation?
Yes, the LPC55S36JBD100K supports crystal-less USB Full-Speed device mode using its internal 96 MHz FRO and software-based clock calibration, as documented in Application Note AN13527. This eliminates the need for an external 12 MHz crystal, reducing BOM count and PCB area. The feature is enabled by default in ROM bootloader and supported in NXP's MCUXpresso SDK USB stack.
How many GPIO pins does the LPC55S36JBD100K provide in the HLQFP100 package?
The LPC55S36JBD100K in HLQFP100 package provides 66 general-purpose I/O pins, all accessible via AHB bus for low-latency register access. These include 8 configurable pin interrupts (PINT), two GPIO group interrupts (GINT), and boolean pattern-matching capability across up to 8 pins. Pin functions are software-selectable via IOCON registers, with reset defaults defined per pin in the datasheet.
What security features differentiate the LPC55S36JBD100K from standard Cortex-M33 MCUs?
The LPC55S36JBD100K integrates hardware security features beyond baseline TrustZone®, including PRINCE inline flash encryption, PKC accelerator for ECC/RSA, PUF-based key generation, DICE-compliant device identity, tamper detection with timestamped queue, and Edge Lock Subsystem (ELS) for secure boot attestation. These are implemented in dedicated silicon blocks - not software libraries - ensuring side-channel resistance and deterministic behavior.
Can the LPC55S36JBD100K execute code directly from external Octal/QuadSPI flash?
Yes, the LPC55S36JBD100K supports Execute-in-Place (XIP) from external Octal/QuadSPI flash using its FlexSPI interface with 8 KB cache and dynamic decryption. PRINCE and IPED modules enable real-time decryption of encrypted XIP images, and address remapping allows dual-image boot from external flash - all managed by the ROM bootloader without CPU intervention.
LPC55S36JBD100K Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 100-LQFP
- Series:
- -
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit Single-Core
- Speed:
- 150MHz
- Connectivity:
- CAN FD, Flexcomm, I2C, I3C, SPI, UART/USART, USB2.0
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, PWM, WDT
- Number of I/O:
- 66
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 23x16b; D/A 3x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC55S36JBD100K FAQ
1.How can I place an order for LPC55S36JBD100K through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC55S36JBD100K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC55S36JBD100K reliable?
The price and inventory of LPC55S36JBD100K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC55S36JBD100K is usually 5 days.
3.What payment methods are accepted for LPC55S36JBD100K?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC55S36JBD100K transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC55S36JBD100K?
LPC55S36JBD100K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC55S36JBD100K order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC55S36JBD100K?
For technical support, including LPC55S36JBD100K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC55S36JBD100K requirements.
6.How does Aetrix verify that LPC55S36JBD100K is sourced from the original manufacturer or authorized distributors?
All LPC55S36JBD100K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC55S36JBD100K meets industry standards.
7.What is the process for return or replacement of LPC55S36JBD100K?
All LPC55S36JBD100K units undergo pre-shipment inspection (PSI). If there is an issue with LPC55S36JBD100K, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC55S36JBD100K part is unused and in its original packaging.
Return procedure for LPC55S36JBD100K:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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