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NXP Semiconductors LPC55S36JBD100MP
- Part No.:
- LPC55S36JBD100MP
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
LPC55S36JBD100MP.pdf
- Description:
- IC MCU 32BIT 256KB FLSH 100HLQFP
- Quantity:
- Payment:
- Shipping:
Inventory:826
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Product details
Overview
LPC55S36JBD100MP from NXP Semiconductors is a 32-bit ARM Cortex-M33 microcontroller with TrustZone security, PRINCE flash encryption, PKC cryptographic acceleration, 256 KB on-chip flash, 128 KB SRAM, USB Full-Speed device/host, CAN FD, and 66 GPIOs - deployed in industrial control, secure IoT edge nodes, and automotive body electronics requiring certified boot and runtime integrity.
For engineers reviewing the LPC55S36JBD100MP datasheet, LPC55S36JBD100MP pinout, LPC55S36JBD100MP application, or LPC55S36JBD100MP equivalent, this page delivers verified package mapping (HLQFP100), confirmed security features (PUF, DICE, ECDSA P-256/P-384), real-time crypto acceleration (PRINCE, PKC), analog subsystem specs (16-bit 2.0 Msps ADC, 3×12-bit DAC), and Flexcomm configurable serial interfaces - all validated against NXP Rev. 3.2 datasheet.
Technical Context
The LPC55S36JBD100MP implements ARM TrustZone for hardware-enforced memory isolation between secure and non-secure worlds, enabling secure firmware updates and protected key storage. Its Edge Lock Subsystem (ELS) orchestrates secure boot via ECDSA-signed SB3.1 images and enforces anti-rollback using monotonic counters in CFPA.
It integrates dual DMA controllers (52+16 channels), PowerQuad DSP accelerator with four 4 KB SRAM banks, and FlexSPI with 8 KB cache and dynamic decryption for XIP from encrypted external flash. The PRINCE module supports up to three internal flash encryption regions and four external regions via IPED.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M33 @ 150 MHz with TrustZone, FPU, MPU, and NVIC - enables deterministic real-time control with secure partitioning. |
| Memory | 256 KB flash (246 KB usable), 128 KB SRAM (16 KB Code Bus + 112 KB System Bus) - supports dual-image boot and large secure firmware payloads. |
| Crypto Acceleration | PRINCE (real-time flash encryption/decryption), PKC (ECC/RSA), AES-256-GCM, SHA-256/384, PUF, TRNG - offloads cryptographic operations from CPU for low-latency secure boot and OTA updates. |
| Analog Peripherals | Four 16-bit ADCs (2.0 Msps), three 12-bit DACs (1.0 Msps), four comparators, three OpAmps - enables high-fidelity sensor acquisition and analog actuation without external ICs. |
| Serial Interfaces | Eight Flexcomm interfaces (configurable as USART/SPI/I2C/I2S), one I3C, one CAN FD, USB FS host/device (crystal-less) - provides flexible connectivity for multi-protocol edge gateways. |
| Timers & PWM | Five 32-bit general-purpose timers, SCTimer/PWM (16 match/capture registers), two FlexPWM (24 outputs), MRT, WWDT - supports motor control, precise timing, and watchdog supervision across power modes. |
| Package & Environment | HLQFP100 (14 × 14 × 0.5 mm), −40 °C to +105 °C operating range, VDDIO_1: 1.8–3.6 V, VDDIO_2: 1.08–3.6 V - suitable for harsh industrial and automotive under-hood applications. |
Pinout & Package
Package: HLQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 0.5 mm pitch (SOT1570-5). Pin functions are software-selectable via IOCON registers; default reset state disables pull-ups/pull-downs except on debug pins (PIO0_0, PIO0_2–PIO0_4, PIO0_5, PIO0_9, PIO0_13–PIO0_14).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PIO0_0 / ACMP0_A | GPIO / Analog comparator input A | Configurable digital I/O or ADC/comparator input; enables wake-up from deep power-down when used as analog input. |
| PIO0_2 / TRST | JTAG Test Reset / Flexcomm 3 clock | Boundary scan mode uses TRST; normal operation configures as Flexcomm 3 SCK - supports debug and serial communication on same pin. |
| PIO0_5 / TDI | JTAG Test Data In / CAN0 transmitter | Boot source selection determined jointly with PIO0_7 at reset; also serves as CAN FD TX output - critical for fail-safe bootloader configuration. |
| FLEXSPI0_DATA3 | FlexSPI data line 3 | Part of octal/quad SPI interface supporting execute-in-place from encrypted external flash - enables secure XIP without exposing decrypted code in RAM. |
| USB_DP / USB_DM | USB Full-Speed differential pair | On-chip PHY supports crystal-less USB device mode using internal FRO - eliminates external crystal and reduces BOM cost in space-constrained designs. |
Key Features
| Feature | Design Value |
|---|---|
| Secure Boot Architecture | ECDSA P-256/P-384 signature verification of SHA-256/384 digests, revocable Root of Trust keys, anti-rollback via monotonic Secure_FW_Version counter - ensures only authenticated, un-reverted firmware executes. |
| Hardware Crypto Acceleration | PRINCE encrypts/decrypts flash reads/writes in real time; PKC performs ECC point multiplication in <100 µs; AES-256-GCM runs at full CPU speed - reduces boot time and enables high-throughput encrypted OTA. |
| Flexible Serial Connectivity | Eight Flexcomm interfaces each configurable as USART/SPI/I2C/I2S; Flexcomm 6–7 support four I2S channel pairs - allows simultaneous audio streaming, sensor comms, and debug over shared pins. |
| Analog Signal Chain Integration | Four 16-bit ADCs with simultaneous conversion capability, integrated temperature sensors, three OpAmps with programmable VREF - enables closed-loop control and sensor fusion without external signal conditioning. |
| Power Management | Deep power-down mode with RAM retention, Micro-Tick Timer wake-up from sleep/deep-sleep, RTC wake-up from all low-power states - achieves sub-µA standby current for battery-powered edge devices. |
Applications
| Industrial PLC Controller | Secure Smart Meter |
|---|---|
Use Scenario: Programmable logic controller managing motor drives, I/O expansion, and fieldbus communication in factory automation. IC Role / Device Role / Timing Role: Main application processor executing real-time control tasks, hosting Modbus TCP/RTU stack, and managing CAN FD fieldbus interface. Use Value: SCTimer/PWM and FlexPWM deliver precise 3-phase motor control; PRINCE and PUF protect firmware and metering algorithms from tampering. | Use Scenario: Electricity meter with tamper detection, secure firmware updates, and HAN communication via I2C/I3C. IC Role / Device Role / Timing Role: Secure system-on-chip handling metrology calculations, cryptographic signing of consumption logs, and secure HAN gateway functions. Use Value: Tamper detection inputs and enhanced tamper queue with timestamping meet IEC 62056 requirements; DICE-compliant boot establishes chain of trust for regulatory certification. |
| Automotive Body Control Module | Audio Edge Gateway |
Use Scenario: Centralized body electronics unit controlling lighting, door locks, and HVAC in 12 V vehicle architectures. IC Role / Device Role / Timing Role: Safety-aware MCU managing CAN FD communication with ECU cluster, executing ASIL-B compliant diagnostics and power sequencing. Use Value: TrustZone isolates safety-critical diagnostics from infotainment services; CRC engine and WWDT ensure functional safety compliance per ISO 26262. | Use Scenario: Voice-enabled IoT gateway aggregating audio from DMIC arrays and forwarding to cloud via USB or CAN FD. IC Role / Device Role / Timing Role: Audio subsystem controller running Voice Activation Detect, decimating DMIC streams, and routing to I2S or USB audio class. Use Value: Dedicated DMIC interface with DMA support processes two-channel PDM at 1.25 MHz; PowerQuad accelerates FFT-based voice processing without CPU load. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar secure microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC55S28JBD100E | Same core, package, and peripheral set but with 128 KB flash and no PRINCE module - lacks real-time flash encryption. | Suitable for cost-sensitive applications where secure boot suffices but encrypted firmware-at-rest is not required. | Select when flash size and crypto acceleration are secondary to BOM cost reduction. |
| RA6M5GFPMXXFA | Renesas RA6M5 with Cortex-M33, 1 MB flash, 384 KB SRAM, but no PKC or PRINCE - relies on software crypto and external secure element for advanced cryptography. | Better suited for high-memory applications needing USB HS, Ethernet, or larger RTOS footprints - less optimized for ultra-low-latency crypto offload. | Choose when extended memory, peripheral count, or Renesas ecosystem integration outweighs NXP's hardware-accelerated security stack. |
Compared with LPC55S28JBD100E and RA6M5GFPMXXFA, the LPC55S36JBD100MP uniquely combines PRINCE flash encryption, PKC hardware acceleration, and DICE-compliant boot in a single HLQFP100 package - delivering lowest-latency secure firmware update and strongest protection for intellectual property in resource-constrained edge nodes.
Availability
LPC55S36JBD100MP is available at Aetrix Electronics and suitable for industrial control systems, secure smart meters, and automotive body electronics requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for safety-critical deployments.
Supply support for LPC55S36JBD100MP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The LPC55S3x product line targets secure edge intelligence applications, integrating ARM TrustZone, hardware crypto accelerators, and robust analog peripherals to simplify development of certified, tamper-resistant embedded systems.
FAQ
What is the maximum operating frequency of the LPC55S36JBD100MP?
The LPC55S36JBD100MP operates at a maximum CPU frequency of 150 MHz using its ARM Cortex-M33 core. This speed is achievable with PLL0 or PLL1 clock sources derived from the internal 12 MHz FRO, external crystal (16–32 MHz), or 32.768 kHz RTC oscillator - enabling deterministic real-time performance for motor control and signal processing tasks within the LPC55S36JBD100MP.
Does the LPC55S36JBD100MP support crystal-less USB operation?
Yes, the LPC55S36JBD100MP supports crystal-less USB Full-Speed device mode using its internal Free Running Oscillator (FRO) and software library examples documented in NXP Application Note AN13527. This eliminates the need for an external 12 MHz crystal, reducing BOM cost and PCB area while maintaining USB compliance - a confirmed capability of the LPC55S36JBD100MP.
How many ADC channels does the LPC55S36JBD100MP support, and what are their resolution and sampling rates?
The LPC55S36JBD100MP integrates four 16-bit ADCs capable of 2.0 Msamples/sec in 16-bit mode or 3.2 Msamples/sec in 12-bit mode, with support for four simultaneous conversions. It offers eight differential channel pairs (or 16 single-ended channels), and both ADCs connect to integrated temperature sensors - specifications directly confirmed for the LPC55S36JBD100MP in NXP's Rev. 3.2 datasheet.
What security features are implemented in hardware on the LPC55S36JBD100MP?
The LPC55S36JBD100MP implements ARM TrustZone, PRINCE flash encryption/decryption, PKC for ECC/RSA, AES-256-GCM, SHA-256/384, Physical Unclonable Function (PUF), True Random Number Generator (TRNG), and Device Identifier Composition Engine (DICE) - all as dedicated hardware blocks. These features enable certified secure boot, runtime firmware protection, and cryptographic key generation unique to the LPC55S36JBD100MP silicon.
What is the package type and pin count of the LPC55S36JBD100MP?
The LPC55S36JBD100MP is packaged in a HLQFP100 plastic low-profile quad flat package with 100 leads, measuring 14 × 14 × 0.5 mm (SOT1570-5). This package is explicitly listed in Table 1 of the NXP datasheet for the LPC55S36JBD100MP ordering variant and supports all I/O, power, and thermal requirements specified for the device.
LPC55S36JBD100MP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 100-LQFP
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit Single-Core
- Speed:
- 150MHz
- Connectivity:
- CAN FD, Flexcomm, I2C, I3C, SPI, UART/USART, USB2.0
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, PWM, WDT
- Number of I/O:
- 66
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 23x16b; D/A 3x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC55S36JBD100MP FAQ
1.How can I place an order for LPC55S36JBD100MP through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC55S36JBD100MP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC55S36JBD100MP reliable?
The price and inventory of LPC55S36JBD100MP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC55S36JBD100MP is usually 5 days.
3.What payment methods are accepted for LPC55S36JBD100MP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC55S36JBD100MP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC55S36JBD100MP?
LPC55S36JBD100MP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC55S36JBD100MP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC55S36JBD100MP?
For technical support, including LPC55S36JBD100MP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC55S36JBD100MP requirements.
6.How does Aetrix verify that LPC55S36JBD100MP is sourced from the original manufacturer or authorized distributors?
All LPC55S36JBD100MP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC55S36JBD100MP meets industry standards.
7.What is the process for return or replacement of LPC55S36JBD100MP?
All LPC55S36JBD100MP units undergo pre-shipment inspection (PSI). If there is an issue with LPC55S36JBD100MP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC55S36JBD100MP part is unused and in its original packaging.
Return procedure for LPC55S36JBD100MP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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