NXP Semiconductors LPC55S36JHI48E

Overview

LPC55S36JHI48E from NXP Semiconductors is a 32-bit ARM Cortex-M33 microcontroller with TrustZone security, PRINCE flash encryption, PKC cryptographic accelerator, 256 KB on-chip flash, 128 KB SRAM, and support for CAN FD, USB Full-Speed device/host, FlexSPI with dynamic decryption, and eight Flexcomm interfaces configurable as USART/SPI/I²C/I²S. It targets secure edge-node applications in industrial control and IoT gateways.

For engineers reviewing the LPC55S36JHI48E datasheet, LPC55S36JHI48E pinout, LPC55S36JHI48E application, or LPC55S36JHI48E equivalent, key selection criteria include its HVQFN48 package footprint, 150 MHz CPU frequency, dual DMA controllers (52+16 channels), hardware-accelerated AES-256/SHA2/PUF/TRNG, and 32 GPIO pins with secure interrupt routing and tamper detection.

Technical Context

The LPC55S36JHI48E implements ARM TrustZone to isolate secure and non-secure execution environments, with dedicated Edge Lock Subsystem (ELS) managing cryptographic key lifecycle and secure boot enforcement via ECDSA P-256/P-384 signatures and SB3.1 firmware update format. Its PRINCE module enables real-time encryption/decryption of internal flash regions and external Octal/QuadSPI memory through inline IPED.

Security is reinforced by a Physical Unclonable Function (PUF) generating 64–4096-bit keys from SRAM fingerprinting, AES-256-GCM engine fed directly from PUF, SHA2-256/384 hardware accelerator with DMA, and tamper detection supporting four filtered external inputs with timestamped queue. The PowerQuad DSP accelerator offloads fixed/floating-point math using four 4 KB SRAM banks accessible by CPU and DMA.

Key Specifications

Pinout & Package

HVQFN48 package: thermally enhanced, leadless, 48-terminal square body with exposed thermal pad. Pin 1 marked by dot; pin numbering clockwise from top-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar secure microcontroller applications.

Compared with LPC55S28JHI48 and RA6M5GFP48FB, the LPC55S36JHI48E uniquely combines PRINCE flash encryption, PUF-derived keys, PKC acceleration, and CAN FD in an HVQFN48 package-enabling secure, fieldbus-connected edge nodes without external crypto co-processors or layout changes.

Availability

LPC55S36JHI48E is available at Aetrix Electronics and suitable for industrial automation, secure IoT gateways, and smart energy metering requiring stable component supply across extended temperature ranges (−40 °C to +105 °C) and long product lifecycles.

Supply support for LPC55S36JHI48E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.

The LPC55S3x product line delivers scalable, TrustZone-enabled microcontrollers designed for secure edge intelligence-integrating hardware crypto accelerators (PRINCE, PKC, PUF), robust peripheral sets, and low-power operation for resource-constrained endpoints.

FAQ

What is the maximum operating frequency of the LPC55S36JHI48E?

The LPC55S36JHI48E features an ARM Cortex-M33 core running at up to 150 MHz. This frequency is achieved using internal PLLs driven by the 12 MHz FRO or external crystal oscillator. The device maintains timing integrity across its full operating temperature range (−40 °C to +105 °C) and supports dynamic voltage scaling to optimize performance versus power consumption in LPC55S36JHI48E designs.

Does the LPC55S36JHI48E support crystal-less USB operation?

Yes, the LPC55S36JHI48E supports crystal-less USB Full-Speed device mode using its internal 48 MHz FRO trimmed to ±0.25% accuracy. This eliminates the need for an external 48 MHz crystal, reducing BOM cost and PCB area. The required firmware library (AN13527) is provided by NXP and integrates seamlessly with the LPC55S36JHI48E ROM bootloader and USB stack.

How many GPIO pins does the LPC55S36JHI48E provide in the HVQFN48 package?

The LPC55S36JHI48E provides 32 GPIO pins in the HVQFN48 package. These include support for secure interrupt routing (PINT), group interrupts (GINT), AOI combinatorial logic, and tamper detection inputs. All GPIO registers reside on the AHB bus for low-latency access, and DMA can directly manipulate GPIO ports-enabling high-speed bit-banging or protocol emulation in LPC55S36JHI48E applications.

What cryptographic accelerators are integrated into the LPC55S36JHI48E?

The LPC55S36JHI48E integrates PRINCE (flash encryption/decryption), PKC (public-key cryptography), AES-256-GCM, SHA2-256/384, PUF (physical unclonable function), TRNG (true random number generator), and DICE v2.0. These accelerators operate independently of the CPU, enabling concurrent secure boot validation, TLS handshake offload, and key derivation without compromising real-time performance in LPC55S36JHI48E deployments.

Is the LPC55S36JHI48E pin-compatible with other LPC55S3x variants in HVQFN48?

Yes, all LPC55S3x devices in the HVQFN48 package-including LPC55S36JHI48E, LPC55S36JHI48, and LPC55S28JHI48-are pin-compatible. They share identical pin functions, electrical characteristics, and thermal pad layout. This allows direct substitution during prototyping or qualification, though firmware must be validated for feature differences such as PRINCE, PKC, or CAN FD presence before deploying LPC55S36JHI48E in production.