NXP Semiconductors LPC55S36JHI48K
- Part No.:
- LPC55S36JHI48K
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
LPC55S36JHI48K.pdf
- Description:
- IC MCU 32BIT 256KB FLSH 48HVQFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,280
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Product details
Overview
LPC55S36JHI48K from NXP Semiconductors is a 32-bit ARM Cortex-M33 microcontroller with TrustZone security, PRINCE flash encryption, PKC cryptographic acceleration, 256 KB on-chip flash, 128 KB SRAM, and support for CAN FD, USB Full-Speed (device/host), FlexSPI with dynamic decryption, and eight Flexcomm interfaces configurable as USART/SPI/I²C/I²S. It targets secure industrial control, IoT edge nodes, and automotive body electronics requiring certified boot and runtime integrity.
For engineers reviewing the LPC55S36JHI48K datasheet, LPC55S36JHI48K pinout, LPC55S36JHI48K application, or LPC55S36JHI48K equivalent, key selection criteria include its HVQFN48 package footprint, 150 MHz CPU frequency, dual DMA controllers (52+16 channels), 32 GPIOs, integrated PUF and TRNG, and absence of CAN FD physical layer support in this variant.
Technical Context
The LPC55S36JHI48K implements ARM TrustZone to isolate secure and non-secure execution environments, with ELS (EdgeLock Subsystem) managing cryptographic key lifecycle and secure boot enforcement via ECDSA P-256/P-384 signatures and SHA-256/384 hashing. Its PowerQuad DSP accelerator offloads fixed/floating-point math using four dedicated 4 KB SRAM banks accessible by CPU and DMA.
Security is enforced through PRINCE real-time flash encryption (up to three internal regions), PKC hardware-accelerated ECC/RSA operations, AES-256-GCM engine fed by PUF-derived keys, and tamper detection with four external inputs filtered by RTC. The device lacks USB Host PHY in HVQFN48 - only USB Device mode is supported with crystal-less operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M33 @ up to 150 MHz with FPU, MPU, and TrustZone isolation |
| Memory | 256 KB flash (246 KB usable), 128 KB SRAM (16 KB code bus + 112 KB system bus) |
| Security | PRINCE flash encryption, PKC module, PUF, TRNG, DICE-compliant Secure Boot (SB3.1), ECDSA P-256/P-384 |
| Peripherals | 8 Flexcomm interfaces (USART/SPI/I²C/I²S), CAN FD controller (no PHY), USB FS Device (crystal-less), FlexSPI with 8 KB cache |
| Analog | 4-channel 16-bit ADC (2.0 Msps), 3× 12-bit DAC (1 Msps), 4 comparators, 3 OpAmps (only OPAMP0_Out routed to pin) |
| Package | HVQFN48, 7 mm × 7 mm × 0.85 mm, thermal pad, 0.4 mm pitch |
| GPIO & Timers | 32 GPIO pins, five 32-bit general-purpose timers, SCTimer/PWM, MRT, WWDT, RTC with calendar and wake-up |
Pinout & Package
HVQFN48 package with exposed thermal pad; 48 terminals arranged in 6×6 grid (excluding corner pads); RoHS-compliant, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PIO0_0 | General-purpose I/O / ACMP0 input A | Default reset state = high-impedance; enables analog comparator input when ANAMODE=1 and DIGIMODE=0 |
| PIO0_1 | General-purpose I/O / ADC1 channel 2B | Supports single-ended or differential ADC input paired with PIO0_13 on ADC1 |
| PIO0_2 | SWCLK / TRST / FC3_TXD | Serial Wire Debug clock input; boundary scan test reset; Flexcomm 3 UART transmit |
| PIO0_3 | TCK / FC3_RXD / CTIMER0_MAT1 | JTAG test clock; Flexcomm 3 UART receive; timer match output for interrupt generation |
| PIO0_4 | TMS / CAN0_RD / FC4_SCK | JTAG mode select; CAN FD receiver input; Flexcomm 4 SPI/I²C clock source |
| PIO0_5 | TDI / CAN0_TD / Boot select | JTAG data input; CAN FD transmitter output; boot source determined jointly with PIO0_7 at reset |
Key Features
| Feature | Design Value |
|---|---|
| Secure Boot Enforcement | ECDSA-signed SB3.1 images verified against up to four revocable Root-of-Trust keys stored in protected flash region (PFR) |
| Runtime Cryptographic Offload | PKC module accelerates ECC point multiplication and RSA modular exponentiation using dedicated 4 KB SRAM banks |
| Flash Protection | PRINCE encrypts/decrypts flash reads/writes inline; supports three independent encrypted regions with key isolation |
| Digital Signal Processing | PowerQuad coprocessor executes FFT, FIR, matrix math, and CMSIS-DSP functions without CPU intervention |
| Low-Power Wake-Up | RTC (32.768 kHz) and Micro-Tick Timer (FRO 1 MHz) independently wake device from deep power-down with 1 ms and sub-ms resolution |
Applications
| Industrial PLC Edge Node | Secure IoT Gateway |
|---|---|
Use Scenario: Local programmable logic control in factory automation with firmware updates over TLS-secured MQTT. IC Role / Device Role / Timing Role: Main application processor executing real-time control loops, validating signed firmware images, and managing encrypted OTA updates via FlexSPI-connected QSPI flash. Use Value: PRINCE and SB3.1 prevent unauthorized firmware execution; 32-bit timers and SCTimer/PWM enable precise motor phase timing within ±100 ns jitter. | Use Scenario: Battery-powered sensor aggregator collecting data from BLE/Wi-Fi endpoints and forwarding to cloud with end-to-end encryption. IC Role / Device Role / Timing Role: Secure root-of-trust host managing PUF-derived session keys, TRNG-sourced nonces, and AES-GCM encryption of payloads before transmission. Use Value: Integrated PUF eliminates external secure element; low-power RTC and Micro-Tick Timer extend battery life beyond 5 years in sleep mode. |
| Automotive Body Controller | Medical Diagnostic Handheld |
Use Scenario: Centralized door/window/mirror control unit requiring ASIL-B compliance and anti-tamper logging. IC Role / Device Role / Timing Role: Safety-monitored MCU running lockstep-capable software, detecting physical intrusion via four external tamper inputs with timestamped queue storage. Use Value: Tamper queue stores event type and timestamp (excluding year) in always-on domain; CRC engine validates configuration memory integrity during startup. | Use Scenario: Portable ultrasound or ECG device needing high-fidelity analog acquisition and HIPAA-compliant data export. IC Role / Device Role / Timing Role: Signal acquisition controller synchronizing 16-bit ADC sampling (2.0 Msps), DMIC voice activation, and I²S audio streaming to external codec. Use Value: Four simultaneous ADC conversions capture multi-channel bio-signals; Flexcomm 6/7 provide four I²S channel pairs for stereo+auxiliary audio paths. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar secure microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC55S28JHI48 | Same HVQFN48 package, but 128 KB flash, 64 KB SRAM, no PRINCE or PKC modules | Lacks hardware-accelerated flash encryption and public-key crypto; suitable for cost-sensitive, lower-security designs | Select when full SB3.1 boot chain and runtime ECC acceleration are not required |
| LPC55S69JBD100 | HLQFP100 package, 256 KB flash, 128 KB SRAM, includes CAN FD PHY and USB Host PHY | Supports CAN FD transceiver interface and USB host stack out-of-box; larger footprint and higher pin count | Choose when CAN FD physical layer connectivity or USB peripheral hosting is mandatory |
Compared with LPC55S28JHI48, the LPC55S36JHI48K adds PRINCE, PKC, and PUF for certified secure boot and runtime key protection; compared with LPC55S69JBD100, it trades CAN FD PHY and USB Host capability for smaller HVQFN48 footprint and lower BOM cost in space-constrained edge devices.
Availability
LPC55S36JHI48K is available at Aetrix Electronics and suitable for industrial control systems, secure IoT gateways, and automotive body electronics requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for LPC55S36JHI48K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with headquarters in Eindhoven, Netherlands.
The LPC55S3x product line delivers scalable, TrustZone-enabled MCUs optimized for secure edge intelligence - integrating cryptographic accelerators, tamper resilience, and low-power mixed-signal peripherals for trusted endpoint deployment.
FAQ
Does LPC55S36JHI48K support USB Host functionality?
No, the LPC55S36JHI48K variant does not integrate a USB Full-Speed Host PHY. It supports USB Full-Speed Device mode only, including crystal-less operation using the internal FRO. USB Host capability requires the LPC55S69JBD100 variant with integrated USB Host PHY and HLQFP100 package.
What is the maximum ADC sampling rate achievable on LPC55S36JHI48K?
The LPC55S36JHI48K supports up to 2.0 Msamples/sec in 16-bit mode across four simultaneous channels, or 3.2 Msamples/sec in 12-bit mode. This performance is enabled by dual independent ADC sequences with hardware-triggered synchronization and DMA-driven data transfer to SRAM.
How many GPIO pins are available on the LPC55S36JHI48K in HVQFN48 package?
The LPC55S36JHI48K provides 32 GPIO pins in the HVQFN48 package. These include multiplexed functions such as ADC inputs, Flexcomm interfaces, PWM outputs, and secure GPIOs. Pin assignments are configured via IOCON registers and documented in Table 3 of the datasheet.
Is PRINCE flash encryption supported on LPC55S36JHI48K?
Yes, the LPC55S36JHI48K fully supports PRINCE real-time flash encryption and decryption. It allows definition of up to three independent encrypted regions in on-chip flash, with keys isolated per region and managed by the ELS subsystem to prevent cross-region access.
Does LPC55S36JHI48K include a CAN FD transceiver?
No, the LPC55S36JHI48K integrates only the CAN FD controller logic - not the physical layer transceiver. External CAN FD transceivers (e.g., TJA1044T) must be used. Unlike the LPC55S69JBD100, this variant lacks integrated CAN FD PHY drivers and related pinmux support for direct bus connection.
LPC55S36JHI48K Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 48-VFQFN Exposed Pad
- Series:
- -
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit Single-Core
- Speed:
- 150MHz
- Connectivity:
- CAN FD, Flexcomm, I2C, I3C, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, PWM, WDT
- Number of I/O:
- 32
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 10x16b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount, Wettable Flank
- Supplier Device Package:
LPC55S36JHI48K FAQ
1.How can I place an order for LPC55S36JHI48K through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC55S36JHI48K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC55S36JHI48K reliable?
The price and inventory of LPC55S36JHI48K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC55S36JHI48K is usually 5 days.
3.What payment methods are accepted for LPC55S36JHI48K?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC55S36JHI48K transactions.
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4.How is shipping managed for LPC55S36JHI48K?
LPC55S36JHI48K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC55S36JHI48K order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC55S36JHI48K?
For technical support, including LPC55S36JHI48K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC55S36JHI48K requirements.
6.How does Aetrix verify that LPC55S36JHI48K is sourced from the original manufacturer or authorized distributors?
All LPC55S36JHI48K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC55S36JHI48K meets industry standards.
7.What is the process for return or replacement of LPC55S36JHI48K?
All LPC55S36JHI48K units undergo pre-shipment inspection (PSI). If there is an issue with LPC55S36JHI48K, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC55S36JHI48K part is unused and in its original packaging.
Return procedure for LPC55S36JHI48K:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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