NXP Semiconductors LPC55S66JBD100E

Overview

LPC55S66JBD100E from NXP Semiconductors is a dual-core Arm Cortex-M33 microcontroller with TrustZone security, CASPER crypto accelerator, and PowerQuad DSP engine. It delivers up to 150 MHz CPU0 operation (rev 1B), 256 KB flash, 144 KB SRAM, and supports secure boot, PRINCE flash encryption, and USB FS/HS interfaces. It targets secure IoT edge nodes requiring real-time control, cryptographic processing, and low-power operation.

For engineers reviewing the LPC55S66JBD100E datasheet, LPC55S66JBD100E pinout, LPC55S66JBD100E application, or LPC55S66JBD100E equivalent, key selection considerations include dual-core asymmetric execution, hardware-accelerated ECC/AES/SHA2, 1.0 Msamples/sec 16-bit ADC with simultaneous differential conversion, and HLQFP100 package compatibility with industrial temperature range (–40 °C to +105 °C).

Technical Context

The LPC55S66JBD100E integrates two Arm Cortex-M33 cores: CPU0 (with FPU, MPU, TrustZone, DSP) for main application execution, and CPU1 (no FPU/MPU/TrustZone) for offloading deterministic tasks. Its CASPER co-processor accelerates ECC operations including point multiplication and modular arithmetic, while PowerQuad handles CMSIS-DSP functions like FFT and FIR filtering in fixed/floating-point.

Security is enforced via PRINCE real-time flash encryption, PUF-derived key generation (64–4096 bits), TRNG, SHA2-AES hardware engine, and DICE-compliant device identity. Clocking includes dual FROs (96 MHz ±1% and 32 kHz ±2%), PLLs, and crystal oscillator support (16–32 MHz and 32.768 kHz), enabling precise timing across power modes.

Key Specifications

Pinout & Package

HLQFP100 package: 100-pin plastic low-profile quad flat package (SOT1570-3), body size 14 × 14 × 0.5 mm, 0.5 mm pitch, exposed thermal pad. Pin 1 index located at top-left corner per JEDEC standard.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core secure microcontroller applications.

Compared with LPC55S69JBD100, the LPC55S66JBD100 trades memory capacity for cost-sensitive designs where 256 KB flash suffices; versus RA6M5GFP, it provides superior ECC acceleration and silicon-rooted key generation ideal for zero-touch provisioning in constrained-edge deployments.

Availability

LPC55S66JBD100E is available at Aetrix Electronics and suitable for industrial PLC edge nodes, secure smart meters, medical sensor hubs, and automotive body controllers requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for LPC55S66JBD100E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in Arm-based microcontrollers and hardware security.

The LPC55S6x product line was designed to deliver scalable, certified security (PSA Certified Level 3, SESIP) and real-time performance in a single chip for resource-constrained edge devices requiring cryptographic agility and functional safety compliance.

FAQ

What is the maximum operating frequency of the LPC55S66JBD100E?

The LPC55S66JBD100E supports up to 150 MHz on its primary Arm Cortex-M33 core (CPU0) and secondary core (CPU1) when using device revision 1B. This frequency is achievable using the internal 96 MHz FRO with PLL0/PLL1 multiplication, eliminating need for external high-frequency crystals in most applications. The LPC55S66JBD100E datasheet specifies this limit under full industrial temperature range (–40 °C to +105 °C) with proper power supply decoupling.

Does the LPC55S66JBD100E support secure boot with public-key verification?

Yes, the LPC55S66JBD100E implements secure boot using RSASSA-PKCS1-v1_5 signatures of SHA256 digests, supporting RSA-2048 and RSA-4096 public keys stored in x509 certificates. It validates up to four revocable Root of Trust keys stored in protected flash, enforces anti-rollback via image key revocation, and complies with TBSA requirements. The LPC55S66JBD100E ROM bootloader performs all verification steps before executing user code.

How does the CASPER co-processor enhance cryptographic performance in the LPC55S66JBD100E?

The CASPER co-processor in the LPC55S66JBD100E provides dedicated hardware acceleration for elliptic curve cryptography (ECC), significantly reducing execution time for ECDSA signing/verification and ECDH key exchange. Benchmarks show >10× speedup over software-only implementations, enabling fast TLS handshake completion and efficient device attestation. The LPC55S66JBD100E integrates CASPER tightly with the memory subsystem to avoid bus contention during crypto operations.

Can the LPC55S66JBD100E operate without an external crystal?

Yes, the LPC55S66JBD100E can operate fully crystal-less using its internal Free Running Oscillators (FROs): a 96 MHz FRO (±1% accuracy over 0–85 °C) for CPU/system clocks and a 32 kHz FRO (±2%) for RTC. USB full-speed device mode supports crystal-less operation via software library TN00063, while high-speed USB requires external 12 MHz crystal. The LPC55S66JBD100E eliminates BOM cost and board space for timing components in many applications.

What ADC capabilities does the LPC55S66JBD100E provide for precision sensing?

The LPC55S66JBD100E features a 16-bit SAR ADC with 10 single-ended or 5 differential input channels, sampling at up to 1.0 Msamples/sec. It supports simultaneous conversions on paired differential channels (e.g., CH1A/CH1B), enabling accurate phase-sensitive measurements. Integrated temperature sensor and programmable gain amplifier (via external circuitry) further enhance precision. The LPC55S66JBD100E ADC includes hardware averaging and flexible trigger sources (timer, DMA, software) for deterministic acquisition.