NXP Semiconductors LPC55S66JBD64E

Overview

LPC55S66JBD64E from NXP Semiconductors is a dual-core Arm Cortex-M33 microcontroller with TrustZone security, CASPER crypto accelerator, and PowerQuad DSP engine-designed for secure embedded control in industrial IoT gateways, smart sensors, and edge AI endpoints. It delivers 150 MHz CPU0 operation (rev 1B), 256 KB flash, 144 KB SRAM, and integrated PRINCE flash encryption.

For engineers reviewing the LPC55S66JBD64E datasheet, LPC55S66JBD64E pinout, LPC55S66JBD64E application, or LPC55S66JBD64E equivalent, key selection criteria include dual-core secure boot support, hardware-accelerated ECC/SHA2/AES, USB FS+HS interface count (36 GPIO), and HTQFP64 package compatibility with industrial temperature range (−40 °C to +105 °C).

Technical Context

The LPC55S66JBD64E integrates two Arm Cortex-M33 cores: CPU0 (with FPU, MPU, TrustZone, DSP) and CPU1 (no FPU/MPU/TrustZone), enabling secure real-time partitioning. Its CASPER co-processor accelerates Elliptic Curve Cryptography, while PowerQuad offloads CMSIS-DSP functions including FFT and filtering.

Security architecture includes PRINCE for on-the-fly flash encryption, PUF-based key generation (64–4096 bits), TRNG, SHA2-AES hardware engine, and DICE-compliant device identity. Clocking supports FRO (±1% @ 0–85 °C), 32 kHz RTC oscillator, and PLLs for flexible frequency synthesis up to 150 MHz.

Key Specifications

Pinout & Package

HTQFP64 package with exposed thermal pad; 64-pin low-profile quad flat package compliant with JEDEC MO-220, RoHS and halogen-free.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core secure MCU applications.

Compared with LPC55S66JBD64E, LPC55S69JBD64 offers double memory capacity without changing PCB layout, while RA6M5GFP64FB trades hardware acceleration for higher base memory-making LPC55S66JBD64E optimal for memory-constrained, crypto-intensive edge nodes.

Availability

LPC55S66JBD64E is available at Aetrix Electronics and suitable for industrial IoT gateways, smart sensor nodes, secure access controllers, and portable medical diagnostics requiring stable component supply across extended product lifecycles.

Supply support for LPC55S66JBD64E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in Arm-based microcontrollers and trusted execution environments.

The LPC55S6x family-including LPC55S66JBD64E-is engineered for secure edge intelligence, combining dual-core Arm Cortex-M33 with hardware crypto, DSP acceleration, and robust power management for resource-constrained embedded systems.

FAQ

What is the maximum CPU frequency supported by LPC55S66JBD64E?

The LPC55S66JBD64E operates at up to 150 MHz on both CPU0 and CPU1 when using device revision 1B. This frequency requires either the internal 96 MHz FRO or PLL configuration; revision 0A parts are limited to 100 MHz. The datasheet specifies this limit under "Ordering Options" Table 2 and confirms it in Section 2.1's General Description.

Does LPC55S66JBD64E support secure boot with RSA-4096 signatures?

Yes, LPC55S66JBD64E supports RSA-4096 public key verification for secure boot using RSASSA-PKCS1-v1_5 signatures of SHA256 digests. It stores root-of-trust keys in protected flash and supports up to four revocable RoT certificates, as documented in Section 2.4 "Secure Boot support" of the datasheet Rev. 2.5.

How many GPIO pins are available on the LPC55S66JBD64E in HTQFP64 package?

The LPC55S66JBD64E provides 36 GPIO pins in the HTQFP64 package, as confirmed in Table 2 "Ordering options" under the "GPIO" column. These include standard and secure GPIOs (SEC_PIOx_y), with up to eight configurable as pin interrupts and two grouped for logical AND/OR wake-up events.

Can LPC55S66JBD64E perform simultaneous ADC conversions on multiple channels?

Yes, LPC55S66JBD64E supports simultaneous conversions on two ADC input channels belonging to the same differential pair-enabled by its 16-bit, 1.0 Msamples/sec ADC with dual-sample-and-hold capability. This is explicitly stated in Section 2.7 "Analog peripherals" and verified in the block diagram (Figure 5).

Is the PRINCE module active by default on LPC55S66JBD64E after reset?

No, the PRINCE module is disabled by default after reset. It must be explicitly enabled and configured via the PFR (Protected Flash Region) registers before use. Encryption/decryption only occurs when PRINCE is activated and region keys are loaded-ensuring flash remains readable until security policy is intentionally applied, per Section 2.2 "On-chip memory".