My Inquiry
My Account
NXP Semiconductors LPC55S69JBD100E
- Part No.:
- LPC55S69JBD100E
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 100-LQFP Exposed Pad
- Datasheet:
-
LPC55S69JBD100E.pdf
- Description:
- IC MCU 32BIT 640KB FLASH 100LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:2,715
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC55S69JBD100E from NXP Semiconductors is a dual-core Arm Cortex-M33 microcontroller with TrustZone security, designed for secure embedded control in industrial IoT and edge AI endpoints. It integrates a 150 MHz primary CPU (CPU0), 150 MHz coprocessor (CPU1), 640 KB flash, 320 KB SRAM, PRINCE flash encryption, CASPER crypto engine, and PowerQuad DSP accelerator - enabling real-time sensor fusion and secure OTA updates in resource-constrained devices.
For engineers reviewing the LPC55S69JBD100E datasheet, LPC55S69JBD100E pinout, LPC55S69JBD100E application, or LPC55S69JBD100E equivalent, this page delivers verified specifications, validated HLQFP100 package mapping, confirmed dual-Cortex-M33 architecture, TrustZone-enabled secure boot flow, and precise alternative part comparisons - all grounded in NXP's Rev. 2.5 datasheet (29 August 2024).
Technical Context
The LPC55S69JBD100E implements two independent Arm Cortex-M33 cores: CPU0 includes MPU, FPU, DSP, ETM, and TrustZone for secure application execution; CPU1 excludes MPU/FPU/TrustZone and serves as a dedicated real-time coprocessor. Both operate up to 150 MHz (device revision 1B) and share access to on-chip memory via multilayer AHB matrix.
Security is enforced through hardware-rooted primitives: PRINCE encrypts flash reads/writes in real time; CASPER accelerates ECC operations; PUF generates and reconstructs keys from 64–4096 bits; SHA-2/AES engines support secure boot with RSA-2048/4096 signature verification and DICE-compliant device identity composition.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Architecture | Dual Arm Cortex-M33 cores: CPU0 (MPU/FPU/TrustZone) + CPU1 (no MPU/FPU/TrustZone), both up to 150 MHz |
| Memory | 640 KB on-chip flash with PRINCE real-time encryption; 320 KB SRAM (272 KB contiguous system bus + 32 KB code bus + 16 KB USB SRAM) |
| Security Engines | CASPER crypto co-processor (ECC acceleration), PowerQuad DSP accelerator (CMSIS-DSP), PUF, TRNG, SHA-2/AES, DICE v2.0 |
| Analog Peripherals | 16-bit ADC with 1.0 Msamples/sec sampling rate, simultaneous dual-channel conversion, five differential pairs |
| Serial Interfaces | Nine Flexcomm interfaces (USART/SPI/I2C/I2S configurable); USB 2.0 full-speed + high-speed host/device with crystal-less FS operation |
| Package & Pins | HLQFP100 (14 × 14 × 0.5 mm, 0.5 mm pitch); 64 GPIO pins with secure I/O, eight pin-interrupt-capable inputs, two GPIO group interrupts |
| Power & Temp | Single 1.8–3.6 V supply; -40 °C to +105 °C operating range; integrated DC-DC converter and PMU with deep power-down mode |
Pinout & Package
HLQFP100 plastic low-profile quad flat package (SOT1570-3), 100 leads, body size 14 × 14 × 0.5 mm, 0.5 mm pitch. Pin functions are software-configurable via IOCON registers; default reset state disables pull-ups/pull-downs except on debug and boot-determining pins (e.g., PIO0_5).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PIO0_0 / ACMP0_A | GPIO / Analog comparator input A | Configurable digital I/O or analog comparator input when DIGIMODE=0 and ANAMODE=1 |
| PIO0_5 / TDI | Boot source selector / JTAG test data input | State at reset determines boot source (flash/ISP); enables boundary scan mode when asserted |
| PIO0_11 / ADC0_9 | ADC input channel 1B / debug clock | Single-ended ADC CH1B or negative differential input paired with CH1A; SWCLK default after boot |
| FC3_SCK | Flexcomm 3 serial clock | Shared clock for USART/SPI/I2S; supports fractional baud-rate generation and timeout features |
| SD0_CMD | SD/MMC 0 command line | Bi-directional command interface for SD2.0/SDR25 cards with DMA support and dual-card capability |
Key Features
| Feature | Design Value |
|---|---|
| TrustZone-enabled dual-core isolation | Hardware-enforced separation between secure (CPU0) and non-secure (CPU1) execution environments for IP protection |
| PRINCE real-time flash encryption | On-the-fly AES-128 encryption/decryption of flash reads/writes without software overhead or latency penalty |
| CASPER crypto acceleration | Hardware execution of elliptic curve cryptography (ECC) operations, reducing key exchange time by >10× vs. software-only implementation |
| PowerQuad DSP engine | Fixed/floating-point CMSIS-DSP function acceleration (e.g., FFT, FIR) with SDK API integration for deterministic signal processing |
| Secure boot with DICE v2.0 | Device Identifier Composition Engine compliant with TCG Family 2.0 Level 00 Rev 69 for cryptographically verifiable device identity |
| Programmable Logic Unit (PLU) | Configurable combinatorial/sequential logic network supporting small state machines without CPU intervention |
Applications
| Industrial PLC Edge Node | Secure Medical Sensor Hub |
|---|---|
Use Scenario: Real-time motor control and fieldbus gateway in compact programmable logic controllers with firmware update over cellular link. IC Role / Device Role / Timing Role: Dual-core coordination: CPU0 handles Modbus TCP stack and secure OTA validation; CPU1 executes deterministic PWM timing via SCTimer/PWM with 16-match register precision. Use Value: PRINCE-encrypted flash prevents unauthorized firmware modification; PowerQuad accelerates vibration analysis FFTs at <10 µs latency. |
Use Scenario: Multi-parameter patient monitor aggregating ECG, SpO₂, and temperature data with HIPAA-compliant local storage and encrypted cloud upload. IC Role / Device Role / Timing Role: Secure boot validates SB2-signed firmware; PUF-derived keys encrypt ADC samples in SRAM before AES-256 transmission; RTC maintains audit log timestamps across power cycles. Use Value: CASPER accelerates ECDSA signing of medical data packets; TRNG feeds entropy into TLS handshakes for TLS 1.3 compliance. |
| Smart Grid Endpoint Meter | Automotive Body Control Module |
Use Scenario: ANSI C12.19-compliant electricity meter with tamper detection, waveform capture, and secure remote configuration. IC Role / Device Role / Timing Role: CPU0 runs DLMS/COSEM stack and SHA-256 hash verification; CPU1 samples 16-bit ADC at 1 MS/s with simultaneous dual-channel capture for harmonic analysis. Use Value: Frequency Measurement Unit validates grid frequency stability; WWDT ensures fail-safe shutdown during voltage sags. |
Use Scenario: CAN FD gateway with secure firmware loading and diagnostic logging in automotive body electronics (e.g., door module, lighting controller). IC Role / Device Role / Timing Role: Flexcomm interfaces configured as UART (diagnostics), SPI (sensor hub), and I2C (EEPROM); secure GPIO isolates critical outputs (e.g., window lift enable). Use Value: Secure boot prevents malicious reprogramming; PLU implements hardware-based window anti-pinch logic independent of CPU scheduling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core secure microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC55S66JBD100 | Same dual-core M33 architecture but reduced memory: 256 KB flash / 144 KB SRAM; no PowerQuad or CASPER | Suitable for cost-sensitive secure boot and basic connectivity where DSP/crypto acceleration is not required | Select when application does not require real-time FFT or ECC acceleration and total memory footprint is ≤256 KB flash |
| RA6M5GFP | Renesas RA6M5 with Cortex-M33, 1 MB flash, 448 KB SRAM, but lacks PRINCE, CASPER, and PowerQuad; uses TrustZone + SCE9 security accelerator | Better suited for high-throughput USB/Ethernet gateways than ultra-low-latency sensor fusion or flash encryption use cases | Choose when larger memory and Ethernet MAC are prioritized over hardware-accelerated crypto/DSP and on-the-fly flash encryption |
Compared with LPC55S66JBD100 and RA6M5GFP, the LPC55S69JBD100 uniquely combines PRINCE flash encryption, CASPER ECC acceleration, and PowerQuad DSP in a single HLQFP100 package - enabling secure, deterministic, and computationally intensive edge workloads without external co-processors or memory expansion.
Availability
LPC55S69JBD100E is available at Aetrix Electronics and suitable for industrial IoT gateways, medical sensor hubs, smart grid meters, and automotive body control modules requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for LPC55S69JBD100E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with headquarters in Eindhoven, Netherlands.
The LPC55S6x product line targets secure, high-performance edge intelligence - integrating dual Cortex-M33 cores, hardware crypto accelerators, and real-time DSP to simplify development of certified secure devices for industrial control and medical applications.
FAQ
What is the maximum operating frequency of the LPC55S69JBD100E?
The LPC55S69JBD100E operates at up to 150 MHz on both its primary Arm Cortex-M33 core (CPU0) and secondary coprocessor core (CPU1), but only for device revision 1B as specified in NXP's Rev. 2.5 datasheet. Revision 0A parts are limited to 100 MHz. The LPC55S69JBD100E's internal PLLs derive this frequency from the 12 MHz FRO or external oscillators, eliminating need for high-frequency crystals.
Does the LPC55S69JBD100E support crystal-less USB full-speed operation?
Yes, the LPC55S69JBD100E supports crystal-less USB full-speed device operation using its internal FRO and software library example documented in NXP Technical Note TN00063. This eliminates external 12 MHz crystal requirements for USB FS functionality while maintaining ±0.25% accuracy - a key advantage for space-constrained designs. The LPC55S69JBD100E also includes a dedicated USB HS PHY for high-speed operation.
How does PRINCE encryption work on the LPC55S69JBD100E?
PRINCE on the LPC55S69JBD100E performs real-time AES-128 encryption of data written to flash and decryption of data read from flash - all in hardware with zero software overhead. Keys are stored in protected flash regions, and the LPC55S69JBD100E enforces strict access control so only authorized secure code can initiate encryption/decryption. This enables secure firmware updates and protects intellectual property without performance penalty.
What security certifications does the LPC55S69JBD100E support out of the box?
The LPC55S69JBD100E implements TBSA (Trusted Board Startup Architecture) compliance, DICE Specification v2.0 Level 00 Rev 69 for device identity, and supports secure boot with RSA-2048/4096 signatures and x.509 certificate validation. It also meets NIST SP 800-193 requirements for platform firmware resilience through anti-rollback, image revocation, and fault analysis mode - all enabled by hardware blocks like PUF, TRNG, and HASH-AES.
Can the LPC55S69JBD100E's ADC perform simultaneous conversions?
Yes, the LPC55S69JBD100E's 16-bit ADC supports simultaneous conversions on two input channels belonging to the same differential pair - for example, CH1A and CH1B - enabling accurate phase-aligned sampling for motor current sensing or audio beamforming. This capability is hardware-synchronized and requires no CPU intervention, delivering true 1.0 Msamples/sec aggregate throughput with deterministic timing.
LPC55S69JBD100E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 100-LQFP Exposed Pad
- Series:
- LPC55S6x
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 150MHz
- Connectivity:
- Flexcomm, I2C, MMC/SD/SDIO, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, PWM, RNG, WDT
- Number of I/O:
- 64
- Program Memory Size:
- 640KB (640K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 320K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 10x16b SAR
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC55S69JBD100E FAQ
1.How can I place an order for LPC55S69JBD100E through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC55S69JBD100E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC55S69JBD100E reliable?
The price and inventory of LPC55S69JBD100E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC55S69JBD100E is usually 5 days.
3.What payment methods are accepted for LPC55S69JBD100E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC55S69JBD100E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC55S69JBD100E?
LPC55S69JBD100E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC55S69JBD100E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC55S69JBD100E?
For technical support, including LPC55S69JBD100E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC55S69JBD100E requirements.
6.How does Aetrix verify that LPC55S69JBD100E is sourced from the original manufacturer or authorized distributors?
All LPC55S69JBD100E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC55S69JBD100E meets industry standards.
7.What is the process for return or replacement of LPC55S69JBD100E?
All LPC55S69JBD100E units undergo pre-shipment inspection (PSI). If there is an issue with LPC55S69JBD100E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC55S69JBD100E part is unused and in its original packaging.
Return procedure for LPC55S69JBD100E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC55S69JBD100E Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
