NXP Semiconductors LPC55S69JBD64E

Overview

LPC55S69JBD64E from NXP Semiconductors is a dual-core Arm Cortex-M33 microcontroller with TrustZone security, 640 KB flash, 320 KB SRAM, and hardware accelerators (CASPER crypto, PowerQuad DSP). It integrates USB FS/HS, SDIO, 16-bit 1.0 Msps ADC, and PRINCE flash encryption-designed for secure industrial edge nodes requiring real-time control and cryptographic integrity.

For engineers reviewing the LPC55S69JBD64E datasheet, LPC55S69JBD64E pinout, LPC55S69JBD64E application, or LPC55S69JBD64E equivalent, key selection considerations include dual-core asymmetric execution, on-the-fly PRINCE encryption, CASPER-accelerated ECC, PowerQuad-optimized CMSIS-DSP, and HTQFP64 package compatibility with 36 GPIOs and full-speed/high-speed USB support.

Technical Context

The LPC55S69JBD64E implements two independent Arm Cortex-M33 cores: CPU0 (with FPU, MPU, TrustZone, ETM) and CPU1 (no FPU/MPU/TrustZone), both operating up to 150 MHz (rev 1B). Its security architecture includes PUF-based key generation, SHA2/AES-256 engines, DICE-compliant secure boot, and PRINCE real-time flash encryption/decryption.

Digital signal processing is accelerated via PowerQuad (fixed/floating-point CMSIS-DSP) and CASPER (ECC, RSA, FFT), while timing subsystems include five 32-bit CTimers, SCTimer/PWM (16 capture/match registers), RTC with 1 ms wake-up resolution, and MRT for multi-rate interrupts-all clocked by configurable FROs (96/12/1 MHz) and crystal oscillators (16–32 MHz, 32.768 kHz).

Key Specifications

Pinout & Package

HTQFP64 package with exposed thermal pad; 64-pin quad flat design optimized for thermal dissipation and PCB routing density in space-constrained industrial modules.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core secure microcontroller applications.

Compared with LPC55S66JBD64, the LPC55S69JBD64E provides 2.5× more flash and 2.2× more SRAM for complex secure firmware and OTA staging; versus RA6M5GFP, it delivers integrated CASPER/PRINCE acceleration eliminating need for external crypto ICs in resource-constrained designs.

Availability

LPC55S69JBD64E is available at Aetrix Electronics and suitable for industrial automation, secure IoT gateways, medical sensor hubs, and automotive body control modules requiring stable component supply across long production lifecycles.

Supply support for LPC55S69JBD64E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in Arm-based microcontrollers and trusted execution environments.

The LPC55S6x product line targets secure, real-time embedded systems demanding hardware-enforced isolation, cryptographic acceleration, and low-power operation-designed specifically for industrial edge intelligence and certified device identity.

FAQ

What is the maximum CPU frequency supported by the LPC55S69JBD64E?

The LPC55S69JBD64E supports a maximum CPU frequency of 150 MHz for both its Arm Cortex-M33 cores (CPU0 and CPU1), but only in device revision 1B. Revision 0A devices are limited to 100 MHz. This frequency is achievable using PLL0 or PLL1 driven by the internal 12 MHz FRO, external crystal (16–32 MHz), or 32.768 kHz RTC oscillator. The LPC55S69JBD64E datasheet specifies this limit under "Ordering Options" and "Clock Generation" sections.

Does the LPC55S69JBD64E support crystal-less USB full-speed operation?

Yes, the LPC55S69JBD64E supports crystal-less USB full-speed device operation using its internal 96 MHz FRO trimmed to ±1% accuracy (for date codes 2041 and later) and software library TN00063. This eliminates the need for an external 12 MHz crystal in USB FS device implementations, reducing BOM cost and board area. The LPC55S69JBD64E USB controller includes an on-chip PHY and dedicated DMA controller to maintain timing compliance without external clocking.

How does the PRINCE module function in the LPC55S69JBD64E?

The PRINCE module in the LPC55S69JBD64E performs real-time AES-128 encryption of data written to on-chip flash and decryption of encrypted data read from flash. It operates transparently in hardware-no CPU intervention required-enabling secure firmware updates and IP protection. Keys are derived from the PUF or supplied via software, and the LPC55S69JBD64E supports booting directly from PRINCE-encrypted flash regions, ensuring confidentiality throughout the entire memory access path.

What are the secure boot capabilities of the LPC55S69JBD64E?

The LPC55S69JBD64E implements secure boot using RSASSA-PKCS1-v1_5 signatures over SHA256 digests, supporting RSA-2048 and RSA-4096 public keys in x509 format. It stores up to four revocable Root of Trust keys in protected flash and enforces anti-rollback via image key revocation. The LPC55S69JBD64E also complies with DICE Specification v2.0 Level 00, generating device-unique identities using PUF and TRNG for zero-touch provisioning and attestation.

Can the LPC55S69JBD64E's dual Cortex-M33 cores run different real-time operating systems?

Yes, the LPC55S69JBD64E's dual Cortex-M33 cores support independent RTOS instances: CPU0 (with TrustZone, FPU, MPU) typically runs a secure OS like TF-M or FreeRTOS with memory protection, while CPU1 (no FPU/MPU/TrustZone) executes a lightweight deterministic RTOS such as Zephyr or bare-metal control loops. Inter-core communication uses the coprocessor interface with mailbox and semaphore hardware, enabling time-critical tasks on CPU1 without compromising CPU0's security partition. This configuration is validated in NXP's LPC55S69 SDK examples.