NXP Semiconductors LPC802M001JHI33E

Overview

LPC802M001JHI33E from NXP Semiconductors is a 32-bit ARM Cortex-M0+ microcontroller operating at up to 15 MHz, featuring 16 KB flash, 2 KB SRAM, a 12-bit ADC with 12-channel input, an analog comparator, and 17 GPIO pins. It integrates UART, SPI, I²C, multi-rate timer, self-wake-up timer, and switch-matrix–based peripheral routing-targeting low-cost embedded control in sensor gateways and portable devices.

For engineers reviewing the LPC802M001JHI33E datasheet, LPC802M001JHI33E pinout, LPC802M001JHI33E application, or LPC802M001JHI33E equivalent, this page delivers verified package mapping (HVQFN33), confirmed pin functions (e.g., PIO0_1/ADC_0/ACMP_I2/CLKIN/TDI), real-world timing roles (WKTCLKIN on PIO0_11), and validated alternatives for industrial and battery-powered designs.

Technical Context

The LPC802M001JHI33E implements an ARM Cortex-M0+ core (r0p1) with single-cycle I/O, nested vectored interrupt controller (NVIC), and Serial Wire Debug (SWD). Its AHB multilayer matrix interfaces flash, SRAM, and APB peripherals including USART0/1, SPI0, I²C0, CTIMER0, and ADC.

Peripheral assignment is fully flexible via the switch matrix: movable functions like U0_TXD, SPI0_MOSI, or I2C0_SCL can be routed to any non-power/non-ground GPIO (PIO0_0 to PIO0_17), while fixed functions-including ADC inputs, comparator pins, SWD, and RESET-are pre-assigned per HVQFN33 pinout. The device supports dual-voltage I/O only in TSSOP20 variants (LPC802M011JDH20); LPC802M001JHI33E uses single-supply operation (VDD only).

Key Specifications

Pinout & Package

HVQFN33 package: 5 mm × 5 mm body, 0.85 mm height, exposed thermal pad (pin 33 = VSS), 33 terminals. Pin 1 index located at top-left corner (see Figure 2 in datasheet). Compatible with reflow soldering; thermal pad must be soldered for reliable power dissipation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar low-cost ARM Cortex-M0+ microcontroller applications.

Compared with LPC802M001JHI33E, LPC804M011JDH20 offers more memory and peripherals but sacrifices HVQFN33 packaging and pin compatibility, while STM32G030F6P6 trades flexibility and analog integration for raw performance and memory - making LPC802M001JHI33E optimal for space-constrained, analog-rich, low-power edge nodes.

Availability

LPC802M001JHI33E is available at Aetrix Electronics and suitable for sensor gateways, industrial control panels, and portable medical monitors requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for LPC802M001JHI33E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with over 40 years of microcontroller innovation.

The LPC800 series targets cost-sensitive, low-power embedded systems requiring high peripheral flexibility and robust analog integration - designed specifically for sensor interfacing, simple motor control, and portable electronics where board space and BOM count are critical.

FAQ

What is the maximum operating frequency of the LPC802M001JHI33E?

The LPC802M001JHI33E operates at a maximum CPU frequency of 15 MHz, derived from its internal Free Running Oscillator (FRO) with selectable 9 MHz, 12 MHz, or 15 MHz outputs trimmed to ±1% accuracy across 0°C to 70°C. This frequency is sufficient for real-time sensor processing and serial communication without external crystal dependency.

Does the LPC802M001JHI33E support dual power supply (VDD/VDDIO)?

No, the LPC802M001JHI33E does not support dual I/O power. Dual supply (VDDIO) is only available on the LPC802M011JDH20 TSSOP20 variant. The LPC802M001JHI33E uses a single VDD supply (1.71–3.6 V) for both core and I/O, with all GPIOs referenced to that rail - simplifying power design but limiting level-shifting capability.

How many ADC channels does the LPC802M001JHI33E support, and what is the resolution?

The LPC802M001JHI33E integrates a 12-bit successive approximation ADC with up to 12 input channels (ADC_0 through ADC_11), supporting sample rates up to 480 kS/s and two independent conversion sequences. Channel selection and trigger sources (internal timers or external events) are configurable via registers - enabling synchronized multi-sensor acquisition.

Can the LPC802M001JHI33E wake up from deep power-down mode using external pins?

Yes, eight GPIO pins (PIO0_4, PIO0_8, PIO0_9, PIO0_10, PIO0_11, PIO0_13, PIO0_15, PIO0_17) can trigger wake-up from deep power-down mode. A LOW-going pulse as short as 50 ns on any of these pins exits deep power-down and resumes execution - critical for ultra-low-power sensor wake-on-event applications.

What debug interface does the LPC802M001JHI33E use, and is JTAG supported?

The LPC802M001JHI33E uses Serial Wire Debug (SWD) as its primary debug interface, accessible via SWDIO (PIO0_2) and SWCLK (PIO0_3). JTAG boundary scan is supported in hardware (TDO/TDI/TCK/TMS on PIO0_0–PIO0_4) but only active in boundary scan mode - SWD is recommended for standard firmware development and programming of the LPC802M001JHI33E.