NXP Semiconductors LPC802M001JHI33Y
- Part No.:
- LPC802M001JHI33Y
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
LPC802M001JHI33Y.pdf
- Description:
- IC MCU 32BIT 16KB FLASH 33HVQFN
- Quantity:
- Payment:

- Shipping:

Inventory:6,000
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Product details
Overview
LPC802M001JHI33Y from NXP Semiconductors is a 32-bit ARM Cortex-M0+ microcontroller operating at up to 15 MHz, featuring 16 KB flash, 2 KB SRAM, a 12-bit ADC with 12-channel input capability, and an analog comparator - deployed in compact HVQFN33 packaging for space-constrained industrial sensor gateways and portable control systems.
For engineers reviewing the LPC802M001JHI33Y datasheet, LPC802M001JHI33Y pinout, LPC802M001JHI33Y application, or LPC802M001JHI33Y equivalent, this page delivers verified technical context, validated pin assignments for the HVQFN33 package, real-world use cases in low-power embedded sensing, and two confirmed alternative MCU options with documented functional and packaging differences.
Technical Context
The LPC802M001JHI33Y integrates an ARM Cortex-M0+ core (r0p1) with single-cycle I/O and a two-stage pipeline, paired with a flexible switch matrix enabling dynamic peripheral-to-pin routing - including USART0/1, SPI0, I2C0, CTIMER0 match/capture, and ADC inputs - all configurable without hardware redesign.
Its power architecture supports four low-power modes (sleep, deep-sleep, power-down, deep power-down), with wake-up capability via 8 dedicated GPIO pins or the self-wake-up timer (WKT) clocked by FRO, internal LPOSc, or external signal - enabling sub-μA operation in battery-powered applications while retaining fast wake latency.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M0+ (r0p1), 15 MHz max - enables deterministic real-time control with <100 ns GPIO toggle and single-cycle multiplier for efficient math operations. |
| Memory | 16 KB flash (EEPROM-based), 2 KB SRAM - sufficient for firmware + data buffers in sensor node firmware with IAP support via ROM API. |
| Analog Peripherals | 12-bit ADC (12 channels, 480 kS/s), 1 analog comparator - supports simultaneous voltage monitoring and threshold-triggered wake-up in climate control systems. |
| Digital Peripherals | 2 USARTs, 1 SPI, 1 I2C (Fast mode), 32-bit CTIMER0, MRT, WWDT - enables multi-protocol communication and precise timing for motor control feedback loops. |
| Power & Clock | 1.71–3.6 V supply, -40°C to +105°C operation, FRO (9/12/15 MHz ±1%), LPOSc (1 MHz) - ensures robust operation across industrial temperature ranges with factory-trimmed clock accuracy. |
| I/O Flexibility | 17 GPIOs with configurable pull-up/down, open-drain, input invert, glitch filter; switch matrix assigns movable functions to non-power pins - eliminates fixed-function pin constraints in PCB layout. |
Pinout & Package
HVQFN33 package: 5 mm × 5 mm × 0.85 mm body, 33-terminal thermal-enhanced quad flat no-lead with exposed thermal pad (pin 33 = VSS). Pin 1 index marked on top-side marking "LPC802M0" line.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | PIO0_1/ADC_0/ACMP_I2/CLKIN/TDI | Primary ADC input 0 and comparator input 2; also accepts external clock or JTAG test data in boundary scan mode. |
| 6 | PIO0_4/ADC_11/TRSTN | ADC input 11 and active-low JTAG reset; default pull-up enables reliable ISP entry when held low during reset. |
| 7 | SWDIO/PIO0_2/TMS | Serial Wire Debug I/O - primary debug interface; TMS function active only in boundary scan mode. |
| 8 | SWCLK/PIO0_3/TCK | Serial Wire Clock - enables SWD programming and debugging without JTAG header footprint. |
| 33 | VSS | Ground reference and thermal pad connection - must be soldered to PCB ground plane for thermal dissipation and noise immunity. |
Key Features
| Feature | Design Value |
|---|---|
| Switch Matrix Routing | Dynamic assignment of USART/SPI/I2C/CTIMER/ADC signals to any non-power GPIO pin - eliminates fixed peripheral pin conflicts and reduces board re-spins. |
| Self-Wake-Up Timer (WKT) | Independent clock domain (FRO/LPOSc/external) enables wake-from-deep-power-down in <10 μs - critical for battery-operated fire sensors requiring ultra-low quiescent current. |
| High-Drive GPIO | Three pins (PIO0_2, PIO0_3, PIO0_12) support 20 mA source drive - directly drives LEDs or small relays without external drivers in lighting and security controllers. |
| Dual-Voltage I/O Support | Not implemented in LPC802M001JHI33Y (no VDDIO pin) - operates as single-supply device; VDD powers all I/Os and core logic. |
| ROM-Based Bootloader | On-chip ROM provides UART-based ISP, Flash IAP, integer divide, and FRO calibration APIs - eliminates need for external programming hardware in production firmware updates. |
Applications
| Sensor Gateway Node | Industrial Climate Controller |
|---|---|
Use Scenario: Compact wireless sensor hub aggregating temperature, humidity, and CO₂ readings from multiple analog/digital sensors before transmitting via UART-to-LoRa module. IC Role / Device Role / Timing Role: Central MCU executing sensor polling, ADC conversion sequencing, data preprocessing, and UART packet framing - coordinated by CTIMER0 and MRT for deterministic timing. Use Value: 12-bit ADC with 12-channel multiplexing and internal trigger sources enables synchronized sampling across 8+ sensors without external mux ICs or timing jitter. |
Use Scenario: Fan speed and HVAC valve control unit responding to local sensor inputs and remote commands over I2C-connected display panel. IC Role / Device Role / Timing Role: Real-time actuator controller using PWM outputs from CTIMER0 match registers and closed-loop feedback via ADC inputs. Use Value: 20 mA GPIO drive capability directly interfaces with opto-isolated triac drivers for fan control - eliminating discrete transistor stages and reducing BOM count. |
| Portable Gaming Peripheral | Fire & Security Input Module |
Use Scenario: Low-latency button/joystick interface for Bluetooth gaming controller with motion sensor fusion and HID report generation. IC Role / Device Role / Timing Role: Input processor handling debounced GPIO interrupts, SPI accelerometer reads, and USB/HID protocol stack - leveraging NVIC priority masking for jitter-free response. Use Value: Single-cycle I/O and NVIC with 4 priority levels ensure sub-50 μs interrupt latency for tactile feedback - meeting strict human-interface responsiveness requirements. |
Use Scenario: Battery-backed smoke detector input conditioner detecting alarm-level analog thresholds and initiating RF alert transmission upon wake-up. IC Role / Device Role / Timing Role: Ultra-low-power monitor using comparator with internal reference and WKT to wake only on valid smoke signal - minimizing average current draw. Use Value: Deep power-down mode with 8 dedicated wake pins and 50 ns pulse detection enables <1 μA standby current while maintaining instant wake capability - extending 10-year battery life. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar low-cost 32-bit MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC804M011JDH20 | Same core, 32 KB flash, 4 KB SRAM, adds second I2C and extra GPIO; TSSOP20 package (20-pin, 4.4 mm width). | Requires larger PCB footprint and different pinout; suited for designs needing expanded memory or dual I2C buses. | Select when firmware growth exceeds 16 KB or dual I2C is required - not drop-in compatible due to pin count and package mismatch. |
| STM32G030F6P6 | ARM Cortex-M0+, 32 MHz max, 32 KB flash, 8 KB SRAM, 12-bit ADC (16 ch), but no comparator; TSSOP20 package. | Lacks analog comparator and switch matrix flexibility; higher clock enables faster computation but increases power in active mode. | Choose for cost-sensitive applications prioritizing raw compute throughput and memory over analog event triggering or pin remapping agility. |
Compared with LPC802M001JHI33Y, LPC804M011JDH20 offers scalable memory and peripherals in a different package, while STM32G030F6P6 trades analog integration and routing flexibility for higher clock speed and larger memory - making LPC802M001JHI33Y optimal for space-constrained, analog-intensive, low-power edge nodes where pin agility matters most.
Availability
LPC802M001JHI33Y is available at Aetrix Electronics and suitable for industrial sensor gateways, portable gaming peripherals, fire and security input modules, and climate control systems requiring stable component supply across extended product lifecycles.
Supply support for LPC802M001JHI33Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications - delivering high-reliability, long-lifecycle components with comprehensive toolchain and ecosystem support.
The LPC800 series targets cost-sensitive, low-power embedded control applications - designed specifically for space-constrained sensor nodes, portable devices, and industrial subsystems requiring rich analog integration and flexible I/O without premium pricing.
FAQ
What is the maximum operating frequency of the LPC802M001JHI33Y?
The LPC802M001JHI33Y operates at a maximum CPU frequency of 15 MHz, enabled by its ARM Cortex-M0+ core (revision r0p1) with a two-stage pipeline and single-cycle I/O. This frequency is achieved using the factory-trimmed Free Running Oscillator (FRO) at 15 MHz ±1% over 0°C to 70°C - providing stable timing for real-time control tasks without external crystal dependency. The LPC802M001JHI33Y does not support overclocking beyond this specification.
Does the LPC802M001JHI33Y support in-system programming (ISP)?
Yes, the LPC802M001JHI33Y supports In-System Programming (ISP) through its USART interface using the on-chip ROM bootloader. During reset, holding PIO0_12 low initiates ISP mode, allowing firmware updates via UART without external debug hardware. The LPC802M001JHI33Y also supports Flash In-Application Programming (IAP) for runtime firmware patching - both features are implemented in the 8 KB boot ROM and require no additional external circuitry.
How many ADC channels does the LPC802M001JHI33Y support, and what is its sampling rate?
The LPC802M001JHI33Y integrates a 12-bit successive-approximation ADC supporting up to 12 input channels (ADC_0 through ADC_11), with sample rates up to 480 kS/s. It supports two independent conversion sequences triggered by software, timers, or peripheral events - enabling synchronized multi-channel acquisition for sensor fusion. The LPC802M001JHI33Y ADC includes internal reference selection and supports external VREFP input up to VDD.
What debug interface does the LPC802M001JHI33Y provide?
The LPC802M001JHI33Y provides Serial Wire Debug (SWD) as its primary debug interface, accessible via SWDIO (PIO0_2) and SWCLK (PIO0_3) pins - requiring only two connections for full programming and real-time debugging. It supports four hardware breakpoints and two watchpoints, and includes JTAG boundary scan (BSDL) for production testing. The LPC802M001JHI33Y does not implement SWO or trace output, and debug functionality remains active across all power modes except deep power-down.
Is the LPC802M001JHI33Y pin-compatible with other LPC802 variants?
No, the LPC802M001JHI33Y is not pin-compatible with TSSOP16, TSSOP20, or WLCSP16 variants due to its HVQFN33 package (33 terminals) - differing in pin count, layout, thermal pad requirement (pin 33 = VSS), and absence of VDDIO. While functional features (flash size, peripherals, clocking) are identical across LPC802M001 variants, PCB design must be specific to HVQFN33 mechanical and routing requirements. The LPC802M001JHI33Y shares no pin mapping with LPC802M001JDH16 or LPC802M001JDH20.
LPC802M001JHI33Y Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 32-VFQFN Exposed Pad
- Series:
- LPC80xM
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+
- Core Size:
- 32-Bit Single-Core
- Speed:
- 15MHz
- Connectivity:
- I2C, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, POR, PWM, WDT
- Number of I/O:
- 17
- Program Memory Size:
- 16KB (16K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 2K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 12x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC802M001JHI33Y FAQ
1.How can I place an order for LPC802M001JHI33Y through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC802M001JHI33Y on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC802M001JHI33Y reliable?
The price and inventory of LPC802M001JHI33Y are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC802M001JHI33Y is usually 5 days.
3.What payment methods are accepted for LPC802M001JHI33Y?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC802M001JHI33Y transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC802M001JHI33Y?
LPC802M001JHI33Y orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC802M001JHI33Y order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC802M001JHI33Y?
For technical support, including LPC802M001JHI33Y datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC802M001JHI33Y requirements.
6.How does Aetrix verify that LPC802M001JHI33Y is sourced from the original manufacturer or authorized distributors?
All LPC802M001JHI33Y products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC802M001JHI33Y meets industry standards.
7.What is the process for return or replacement of LPC802M001JHI33Y?
All LPC802M001JHI33Y units undergo pre-shipment inspection (PSI). If there is an issue with LPC802M001JHI33Y, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC802M001JHI33Y part is unused and in its original packaging.
Return procedure for LPC802M001JHI33Y:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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