NXP Semiconductors LPC804M101JDH20J

Overview

LPC804M101JDH20J from NXP Semiconductors is a 32-bit Arm Cortex-M0+ microcontroller operating at up to 15 MHz, featuring 32 KB flash, 4 KB SRAM, a 12-bit ADC (up to 480 kS/s), 10-bit DAC, and Capacitive Touch Interface - designed for compact sensor gateways and portable control systems.

For engineers reviewing the LPC804M101JDH20J datasheet, LPC804M101JDH20J pinout, LPC804M101JDH20J application, or LPC804M101JDH20J equivalent, this page delivers verified package mapping (TSSOP20), confirmed peripheral count (2×I²C, 2×USART, 1×SPI), GPIO count (17), and functional validation of PLU, self-wake-up timer, and switch-matrix I/O routing.

Technical Context

The LPC804M101JDH20J integrates an Arm Cortex-M0+ core (r0p1) with single-cycle I/O and NVIC, coupled to a multilayer AHB matrix and APB peripherals. Its clock system centers on a ±1% trimmed Free Running Oscillator (9/12/15 MHz) and supports low-power operation via sleep, deep-sleep, and power-down modes with wake-up on USART/SPI/I²C activity.

Peripherals are routed flexibly through a hardware switch matrix: fixed pins (e.g., SWDIO, RESET, ADC inputs) coexist with movable functions (U0_TXD, SPI_MOSI, I²C_SCL), while the Programmable Logic Unit (PLU) enables user-defined combinatorial/sequential logic without CPU intervention.

Key Specifications

Pinout & Package

TSSOP20 package (SOT360-1), 4.4 mm body width, 0.65 mm pitch - surface-mount compatible with standard reflow profiles and accessible for manual prototyping.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microcontroller applications.

Compared with STM32G031F8P6 and RP2040, the LPC804M101JDH20J offers unique integration of Cap Touch, analog comparator, and PLU logic in a compact TSSOP20 package - making it optimal for cost-sensitive, analog-rich embedded control where firmware simplicity and peripheral consolidation are prioritized.

Availability

LPC804M101JDH20J is available at Aetrix Electronics and suitable for sensor gateways, portable control panels, and industrial motor starters requiring stable component supply and long-term industrial-grade availability.

Supply support for LPC804M101JDH20J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT markets.

The LPC804 series targets cost-optimized, low-power 32-bit control applications - emphasizing peripheral integration (Cap Touch, PLU, switch matrix) and simplified design for resource-constrained edge devices.

FAQ

What is the maximum operating frequency of the LPC804M101JDH20J?

The LPC804M101JDH20J operates at a maximum CPU frequency of 15 MHz using its internal Free Running Oscillator (FRO), which is trimmed to ±1% accuracy across 0°C to 70°C. This frequency is fixed and cannot be overclocked; the FRO supports selectable outputs of 9 MHz, 12 MHz, or 15 MHz via configuration registers. The LPC804M101JDH20J does not support external crystal oscillators above 15 MHz.

Does the LPC804M101JDH20J include a DAC, and what is its resolution?

Yes, the LPC804M101JDH20J includes a single 10-bit DAC (DACOUT) routed to PIO0_19 in HVQFN33 packages, but this pin is not present in the TSSOP20 package used by LPC804M101JDH20J. Therefore, the DAC is not accessible on the LPC804M101JDH20J variant - confirmed by Table 2 in the datasheet, which lists "-" for DAC in the LPC804M101JDH20 row.

How many GPIO pins are available on the LPC804M101JDH20J?

The LPC804M101JDH20J provides 17 general-purpose I/O pins (PIO0_0 through PIO0_17), as specified in Table 2 of the datasheet. All 17 pins support configurable pull-up/pull-down resistors, programmable open-drain mode, input inversion, and glitch filtering. Five of these (PIO0_2, PIO0_3, PIO0_12, PIO0_18, PIO0_20) support high-current 20 mA source drive - though PIO0_18 is not bonded out in TSSOP20, leaving four high-drive pins available on LPC804M101JDH20J.

Is the LPC804M101JDH20J pin-compatible with other LPC804 variants?

No, the LPC804M101JDH20J (TSSOP20) is not pin-compatible with LPC804M101JDH24 (TSSOP24) or LPC804M101JHI33 (HVQFN33). Pin counts, layouts, and function mappings differ significantly: TSSOP20 has 20 pins with 17 GPIOs, while TSSOP24 offers 24 pins and HVQFN33 provides 33 terminals. The switch matrix allows functional flexibility within each package, but physical pin assignments and peripheral availability (e.g., DAC, dual I/O supply) vary by variant.

What debug interface does the LPC804M101JDH20J support?

The LPC804M101JDH20J supports Serial Wire Debug (SWD) using dedicated pins SWDIO (PIO0_2) and SWCLK (PIO0_3), with four hardware breakpoints and two watchpoints. JTAG boundary scan is supported via TDO/TDI/TCK/TMS on PIO0_0–PIO0_4, but only in boundary scan mode - SWD is the primary debug interface for firmware development and in-circuit programming of the LPC804M101JDH20J.