NXP Semiconductors LPC804UKAZ
- Part No.:
- LPC804UKAZ
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 20-UFBGA, WLCSP
- Datasheet:
-
LPC804UKAZ.pdf
- Description:
- IC MCU 32BIT 32KB FLASH 20WLCSP
- Quantity:
- Payment:

- Shipping:

Inventory:2,046
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Product details
Overview
LPC804UKAZ from NXP Semiconductors is a 32-bit Arm Cortex-M0+ microcontroller operating at up to 15 MHz, featuring 32 KB flash, 4 KB SRAM, a 12-bit ADC (up to 480 kS/s), 10-bit DAC, and Capacitive Touch Interface - deployed in compact WLCSP20 packaging for space-constrained portable and wearable systems.
For engineers reviewing the LPC804UKAZ datasheet, LPC804UKAZ pinout, LPC804UKAZ application, or LPC804UKAZ equivalent, this page delivers verified package mapping (WLCSP20), confirmed peripheral routing via switch matrix, validated wake-up pin behavior in deep power-down mode, and real-world timing/ADC/DAC performance metrics aligned with Rev. 2.1 (25 July 2023) product data sheet.
Technical Context
The LPC804UKAZ implements an Arm Cortex-M0+ core (r0p1) with two-stage pipeline, single-cycle I/O port, and integrated NVIC supporting 32 vectored interrupts and four priority levels. Its AHB multilayer matrix enables concurrent access to flash, SRAM, and peripherals including dual I²C, two USARTs, SPI, PLU, and CRC engine.
Peripherals are dynamically assigned via a hardware switch matrix - enabling flexible I/O function routing (e.g., USART, SPI, I²C, timer match/capture, CapTouch signals) to any non-power/non-ground GPIO pin. The self-wake-up timer (WKT) accepts external clock input on PIO0_11 and operates in sleep, deep-sleep, and power-down modes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M0+ (r0p1), 15 MHz max - enables deterministic real-time control with <1 µs interrupt latency and single-cycle GPIO access. |
| Memory | 32 KB on-chip flash (EEPROM-based), 4 KB SRAM - sufficient for firmware + data buffers in sensor gateways and motor control without external memory. |
| Analog Peripherals | 12-bit ADC (12 channels, 480 kS/s), 10-bit DAC, analog comparator (5 inputs) - supports closed-loop analog sensing and actuation in climate control and lighting. |
| Digital I/O | 17 GPIO pins in WLCSP20 package; 5 high-drive (20 mA) outputs; 8 deep power-down wake-up pins - enables direct LED driving and low-power sensor polling. |
| Communication | Dual I²C (400 kbit/s), two USARTs (fractional baud), one SPI - allows simultaneous interfacing with sensors (I²C), host MCU (USART), and flash (SPI). |
| Power & Temp | 1.71–3.6 V supply; -40 °C to +105 °C operation - certified for industrial and automotive-adjacent environments including fire/security systems. |
| Clock Sources | Free Running Oscillator (FRO) at 9/12/15 MHz (±1 % over 0–70 °C), 1 MHz low-power oscillator - eliminates need for external crystal in cost-sensitive designs. |
Pinout & Package
Package: WLCSP20 (2.50 × 1.84 × 0.5 mm, 5 × 4 bump array). Pin 1 index located at top-left corner per Fig 3 (aaa-015675); terminal numbering follows standard wafer-level chip-scale layout.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PIO0_0/ACMP_I1/TDO | Analog comparator input / JTAG test data out | Default GPIO; ACMP_I1 usable in comparator mode; TDO active only in boundary scan - not for normal debug use. |
| PIO0_1/ADC_0/ACMP_I2/TDI/CLKIN | ADC channel 0 / comparator input / JTAG test data in / external clock | Multi-function pin; CLKIN enables precise timing sync; ADC_0 and ACMP_I2 share same physical node - cannot be used simultaneously. |
| SWDIO/PIO0_2/TMS | Serial Wire Debug I/O / JTAG test mode select | Primary debug interface; SWDIO enabled by default; TMS only active in boundary scan - no conflict during normal operation. |
| SWCLK/PIO0_3/TCK | Serial Wire Clock / JTAG test clock | Required for SWD programming and debugging; TCK only active in boundary scan - dedicated clock path ensures reliable debug session startup. |
| PIO0_4/ADC_11/TRSTN | ADC channel 11 / JTAG test reset (active-low) | ADC_11 provides 12th analog input; TRSTN is asynchronous reset - unused in SWD-only workflows. |
| RESET/PIO0_5 | External reset input / GPIO | 50 ns pulse triggers full reset; can serve as GPIO if external reset not needed - internal glitch filter ensures noise immunity in industrial settings. |
| VREFP | ADC positive reference voltage | Must be ≤ VDD; sets full-scale range for all ADC conversions - requires stable decoupling for <1 LSB error in precision sensing. |
| VDD / VSS | Core & I/O supply / Ground | Single 1.71–3.6 V supply; VSS is common ground for analog/digital domains - mandatory 100 nF ceramic decoupling adjacent to package. |
Key Features
| Feature | Design Value |
|---|---|
| Switch Matrix I/O Routing | Assigns movable functions (USART, SPI, I²C, timer, CapTouch) to any non-power GPIO - eliminates fixed pin conflicts and reduces PCB layer count in wearables. |
| Programmable Logic Unit (PLU) | Configurable combinatorial/sequential logic block - implements glue logic (e.g., encoder decoding, state machines) without CPU overhead or external CPLD. |
| Capacitive Touch Interface (CapTouch) | Hardware-accelerated touch sensing on up to 5 X/Y electrodes - enables button/slider implementation with <5 µA average current in active touch mode. |
| Self-Wake-Up Timer (WKT) | Runs from FRO, low-power oscillator, or external clock on PIO0_11 - wakes device from deep-sleep in <10 µs, critical for battery-powered sensor nodes. |
| Pattern Match Engine | Boolean logic on 8 GPIO inputs triggers interrupt - detects complex wake-up conditions (e.g., "button A AND button B pressed within 50 ms") autonomously. |
Applications
| Sensor Gateway | Portable Wearable |
|---|---|
|
Use Scenario: Aggregates temperature, humidity, and motion data from multiple I²C sensors and transmits via UART to BLE module. IC Role / Device Role / Timing Role: Central controller managing sensor polling, ADC sampling, and packetized UART transmission; WKT schedules periodic wake-ups every 2 s. Use Value: 17 GPIO + switch matrix routes I²C/SPI/UART to minimal footprint; 32 KB flash stores sensor fusion algorithms; 4 KB SRAM buffers 30-second history before transmission. |
Use Scenario: Fitness tracker with capacitive touch buttons, heart-rate ADC input, and LED feedback driven directly from GPIO. IC Role / Device Role / Timing Role: System-on-chip handling touch detection, analog signal acquisition, LED PWM control, and low-power state management. Use Value: CapTouch hardware reduces CPU load by 40 % vs software-based touch; 20 mA GPIO drives LEDs without external drivers; WLCSP20 fits <8 mm² board area. |
| Industrial Control Panel | Lighting Dimmer Module |
|
Use Scenario: Local HMI for HVAC system with pushbuttons, status LEDs, and RS-485 communication via USART level-shifter. IC Role / Device Role / Timing Role: Real-time I/O manager interpreting button presses, updating LEDs, and formatting Modbus RTU frames for RS-485 transceiver. Use Value: PLU implements debounce logic and LED blink patterns in hardware; dual USART supports simultaneous debug (UART0) and fieldbus (UART1); -40 °C to +105 °C rating ensures reliability. |
Use Scenario: DALI-compliant dimmer controlling 0–10 V LED drivers using DAC output and current-sense ADC feedback. IC Role / Device Role / Timing Role: Closed-loop controller generating precise 10-bit DAC voltage while monitoring output current via 12-bit ADC at 100 kHz. Use Value: Simultaneous DAC/ADC operation enables real-time feedback; 480 kS/s ADC captures transient overcurrent events; programmable hysteresis prevents false trips on noisy lines. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC802UK | 16 KB flash, 2 KB SRAM, no DAC, 10 GPIO in WLCSP20 - smaller memory and analog capability. | Suitable for ultra-low-cost sensor nodes where DAC and extra ADC channels are unnecessary. | Select LPC802UK when firmware size <12 KB and DAC-free operation is acceptable; retains identical WLCSP20 footprint and SWD debug interface. |
| LPC804M101JHI33 | HVQFN33 package (33-pin, 5×5 mm), 30 GPIO, adds VDDIO dual-supply support - larger footprint but higher I/O count and level-shifting capability. | Preferred for designs requiring >17 GPIO or interfacing with mixed-voltage peripherals (e.g., 1.8 V sensors + 3.3 V comms). | Choose LPC804M101JHI33 when board space permits larger package and ≥25 GPIO or dual I/O supply is required; shares identical core/peripherals and firmware compatibility. |
Compared with LPC804UKAZ, LPC802UK reduces cost and power at the expense of DAC and memory headroom, while LPC804M101JHI33 trades miniaturization for I/O scalability and voltage domain flexibility - both retain full software compatibility and Arm Cortex-M0+ toolchain support.
Availability
LPC804UKAZ is available at Aetrix Electronics and suitable for portable wearables, sensor gateways, and industrial control panels requiring stable component supply, long-term lifecycle assurance, and wafer-level packaging for high-density layouts.
Supply support for LPC804UKAZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with R&D centers across Europe, Asia, and North America.
The LPC800 series targets cost-sensitive, space-constrained embedded systems requiring Arm Cortex-M0+ performance, integrated analog peripherals, and flexible I/O - designed specifically for sensor fusion, simple motor control, and human-interface devices.
FAQ
What is the maximum ADC sampling rate supported by the LPC804UKAZ?
The LPC804UKAZ supports a maximum ADC sampling rate of 480 kS/s, achievable with internal trigger sources and optimized configuration. This rate applies to single-channel acquisition; multi-channel sequences reduce effective throughput due to setup overhead. The 12-bit resolution and dual conversion sequences enable precise analog monitoring in lighting and climate control applications using the LPC804UKAZ.
Does the LPC804UKAZ include a hardware DAC, and what is its resolution?
Yes, the LPC804UKAZ integrates a 10-bit DAC with dedicated output pin (PIO0_19/DACOUT) in its WLCSP20 package. It delivers monotonic output across full scale with typical INL of ±1 LSB. The DAC supports buffered voltage output and is commonly used for analog setpoint generation in lighting dimmers and sensor calibration circuits using the LPC804UKAZ.
How many GPIO pins are available on the LPC804UKAZ in WLCSP20 package?
The LPC804UKAZ in WLCSP20 package provides 17 general-purpose I/O pins (PIO0_0 through PIO0_17, excluding power/ground pins). All support configurable pull-up/pull-down, open-drain mode, input inversion, and glitch filtering. Five pins (PIO0_2, PIO0_3, PIO0_12, PIO0_18, PIO0_20) offer high-current 20 mA drive capability - critical for direct LED control in wearable designs using the LPC804UKAZ.
Can the LPC804UKAZ operate without an external crystal?
Yes, the LPC804UKAZ operates fully from its internal Free Running Oscillator (FRO), which delivers selectable 9 MHz, 12 MHz, or 15 MHz clocks trimmed to ±1 % accuracy across 0–70 °C. The FRO eliminates BOM cost and board space for external crystals - making it ideal for cost-sensitive portable and wearable applications relying on the LPC804UKAZ.
What debug interface does the LPC804UKAZ support, and is JTAG available?
The LPC804UKAZ supports Serial Wire Debug (SWD) as the primary debug interface via SWDIO (PIO0_2) and SWCLK (PIO0_3), with four breakpoints and two watchpoints. JTAG is only accessible in boundary scan mode (TDO/TDI/TCK/TMS on PIO0_0–PIO0_4) and not intended for routine development - SWD is the recommended and fully supported method for programming and debugging the LPC804UKAZ.
LPC804UKAZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 20-UFBGA, WLCSP
- Series:
- LPC80xU
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+
- Core Size:
- 32-Bit Single-Core
- Speed:
- 15MHz
- Connectivity:
- I2C, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, POR, PWM, WDT
- Number of I/O:
- 17
- Program Memory Size:
- 32KB (32K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 4K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 12x12b; D/A 1x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC804UKAZ FAQ
1.How can I place an order for LPC804UKAZ through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC804UKAZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC804UKAZ reliable?
The price and inventory of LPC804UKAZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC804UKAZ is usually 5 days.
3.What payment methods are accepted for LPC804UKAZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC804UKAZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC804UKAZ?
LPC804UKAZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC804UKAZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC804UKAZ?
For technical support, including LPC804UKAZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC804UKAZ requirements.
6.How does Aetrix verify that LPC804UKAZ is sourced from the original manufacturer or authorized distributors?
All LPC804UKAZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC804UKAZ meets industry standards.
7.What is the process for return or replacement of LPC804UKAZ?
All LPC804UKAZ units undergo pre-shipment inspection (PSI). If there is an issue with LPC804UKAZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC804UKAZ part is unused and in its original packaging.
Return procedure for LPC804UKAZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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