NXP Semiconductors LPC812M101FDH16FP
- Part No.:
- LPC812M101FDH16FP
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
LPC812M101FDH16FP.pdf
- Description:
- IC MCU 32BIT 16KB FLASH 16TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,781
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC812M101FDH16FP from NXP Semiconductors is a 32-bit ARM Cortex-M0+ microcontroller in TSSOP16 package, operating up to 30 MHz with 16 kB flash and 4 kB SRAM. It integrates three USARTs, two SPI interfaces, one I²C-bus interface, a State Configurable Timer (SCT), CRC engine, and 14 GPIO pins-designed for cost-sensitive embedded control in lighting and motor drive applications.
For engineers reviewing the LPC812M101FDH16FP datasheet, LPC812M101FDH16FP pinout, LPC812M101FDH16FP application, or LPC812M101FDH16FP equivalent, key selection criteria include its switch-matrix–enabled peripheral routing, deep power-down wake-up capability via PIO0_4, 5 V-tolerant I/O with configurable hysteresis, and ROM-based ISP/IAP support for field firmware updates.
Technical Context
The LPC812M101FDH16FP implements an ARM Cortex-M0+ core with single-cycle I/O access and integrated NVIC supporting 32 vectored interrupts-including up to eight external GPIO interrupts with edge/level sensitivity. Its switch matrix enables dynamic assignment of USART, SPI, I²C, and SCT functions to any non-power/non-ground pin, decoupling peripheral logic from fixed pinout constraints.
Power management includes four low-power modes (Sleep, Deep-sleep, Power-down, Deep power-down), with wake-up from Deep power-down triggered by PIO0_4. Clocking supports internal 12 MHz RC oscillator (±1 %), external crystal (1–25 MHz), PLL for CPU rate scaling, and dedicated clock output with programmable divider.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M0+, 30 MHz max - enables deterministic real-time control with low gate count and energy efficiency. |
| Memory | 16 kB flash / 4 kB SRAM - sufficient for standalone sensor fusion or motor commutation firmware without external memory. |
| GPIO Pins | 14 configurable I/O - all 5 V tolerant with pull-up/pull-down, hysteresis, and glitch filtering for robust industrial interfacing. |
| Serial Interfaces | 3 × USART, 2 × SPI, 1 × I²C - full peripheral set for multi-protocol communication; I²C requires PIO0_10/PIO0_11 for open-drain compliance. |
| Timers & Logic | SCT (State Configurable Timer), MRT, WKT, WWDT - SCT enables custom state machines on I/O pins; WKT uses 10 kHz oscillator for ultra-low-power wake-up timing. |
| Power Modes | Deep power-down mode with 100 nA typical current - enables battery-powered operation for years when paired with external wake-up triggers. |
| Debug Interface | SWD (SWDIO/SWCLK on PIO0_2/PIO0_3) - minimal 2-pin debug footprint; JTAG available only in boundary scan mode. |
Pinout & Package
TSSOP16 package (SOT403-1), 4.4 mm body width, 0.65 mm pitch - compatible with standard surface-mount assembly processes and space-constrained PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PIO0_0 | GPIO / ACMP_I1 / TDO | Default GPIO; analog comparator input 1 or SWD test data out during boundary scan - no conflict with active debug or analog use. |
| PIO0_1 | GPIO / ACMP_I2 / CLKIN | ISP entry pin (LOW at reset); accepts external clock source or comparator input - critical for bootloader activation and timing flexibility. |
| PIO0_2 | SWDIO / GPIO / TMS | Default SWD I/O; enables debug without external header - retains GPIO function when SWD disabled via switch matrix. |
| PIO0_3 | SWCLK / GPIO / TCK | Default SWD clock; essential for programming and runtime debugging - shares pin with JTAG clock in boundary scan mode. |
| PIO0_4 | GPIO / WAKEUP / TRST | Dedicated Deep power-down wake-up trigger; LOW pulse ≥50 ns exits deep sleep - must remain unassigned to movable functions for reliable low-power operation. |
| PIO0_5 | RESET / GPIO | Active-low reset input; also serves as GPIO - external pull-up required for Deep power-down mode stability. |
| PIO0_6 | GPIO / VDDCMP | Comparator reference voltage source - enables ratiometric analog sensing without external precision reference. |
| PIO0_7–PIO0_13 | GPIO (14 total) | All 5 V tolerant with configurable pull-up/down and hysteresis - suitable for direct connection to industrial sensors and actuators. |
| VDD / VSS | Power / Ground | Single 3.3 V supply; no separate analog/digital rails - simplifies power design but requires careful noise isolation for mixed-signal use. |
Key Features
| Feature | Design Value |
|---|---|
| Switch Matrix (SWM) | Enables runtime reassignment of USART/SPI/I²C/SCT functions to any GPIO pin - eliminates PCB redesign when interface requirements change. |
| State Configurable Timer (SCT) | Hardware state machine engine with capture/match on assigned pins - replaces software polling for PWM generation, quadrature decoding, or protocol emulation. |
| Pin Interrupt & Pattern Match Engine | Supports boolean logic across 8 GPIO inputs - allows hardware-accelerated event detection (e.g., "button + sensor high") without CPU intervention. |
| ROM API Firmware | Pre-programmed drivers for ISP, IAP, USART, I²C, and power profiles - reduces firmware size and accelerates development of field-upgradable products. |
| Deep Power-Down Mode | 100 nA typical current draw with wake-up via PIO0_4 - extends battery life in remote sensors or security peripherals beyond 10 years. |
Applications
| Lighting Control | Motor Drive Interface |
|---|---|
Use Scenario: Digital dimming and color mixing in LED driver modules using PWM and I²C configuration. IC Role / Device Role / Timing Role: MCU executing closed-loop brightness control, managing thermal feedback, and communicating with master controller via I²C. Use Value: SCT generates precise, jitter-free PWM signals; switch matrix routes I²C to dedicated open-drain pins for bus compliance while freeing other pins for analog sensing. | Use Scenario: BLDC motor commutation sequencing and fault monitoring in fan or pump controllers. IC Role / Device Role / Timing Role: Real-time timer-driven commutation logic with Hall sensor input processing and overcurrent detection. Use Value: MRT provides synchronized interrupt timing for phase switching; GPIO interrupt engine detects edge-triggered Hall transitions with sub-microsecond latency. |
| Climate Sensor Node | Fire/Security Panel Interface |
Use Scenario: Battery-powered temperature/humidity node transmitting data via UART to gateway. IC Role / Device Role / Timing Role: Low-power sensor aggregator with periodic wake-up, ADC sampling, and serial transmission. Use Value: Deep power-down mode with WKT wake-up ensures <1 µA average current; ROM-based USART driver minimizes code footprint for compact firmware. | Use Scenario: Zone monitoring and alarm signaling in commercial fire panels with tamper detection. IC Role / Device Role / Timing Role: Input conditioning, supervised loop monitoring, and relay control with watchdog supervision. Use Value: Windowed Watchdog (WWDT) prevents silent firmware lockup; 5 V-tolerant GPIO handles legacy 24 V dry-contact inputs via resistive dividers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC812M101FDH20 | Same core, 18 GPIO, TSSOP20 package - adds two more I/O pins and second USART channel. | Required when >14 GPIO or dual USART needed; larger footprint increases PCB area and cost. | Select LPC812M101FDH20 only if additional I/O or USART2 functionality is confirmed necessary - LPC812M101FDH16FP suffices for most TSSOP16-constrained designs. |
| LPC811M001FDH16 | Same TSSOP16 package but reduced resources: 8 kB flash, 2 kB SRAM, 2 USART, 14 GPIO. | Suitable for simpler control tasks without SCT or third USART; lacks ROM-based IAP support. | Choose LPC811M001FDH16 for cost-optimized, non-upgradable firmware deployments where flash headroom and peripheral count are lower priorities. |
Compared with LPC812M101FDH20 and LPC811M001FDH16, the LPC812M101FDH16FP delivers optimal balance of I/O count, peripheral richness, and package size - retaining full SCT, three USARTs, and IAP capability within the smallest TSSOP footprint of the LPC81xM family.
Availability
LPC812M101FDH16FP is available at Aetrix Electronics and suitable for lighting control, motor drive interface, and climate sensor node applications requiring stable component supply and long-term industrial availability.
Supply support for LPC812M101FDH16FP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The LPC81xM product line was designed for cost-sensitive, low-power embedded control applications - emphasizing flexible peripheral routing, ultra-low-power operation, and rapid firmware development through ROM-based drivers and intuitive toolchain support.
FAQ
What is the maximum operating frequency of the LPC812M101FDH16FP?
The LPC812M101FDH16FP operates at a maximum CPU frequency of 30 MHz, enabled by its ARM Cortex-M0+ core and internal PLL. This frequency is achievable using the internal 12 MHz RC oscillator, external crystal (1–25 MHz), or CLKIN source - with the PLL configured to scale the clock without requiring a high-frequency crystal. The LPC812M101FDH16FP maintains timing integrity across all supported clock sources per its objective data sheet Rev. 1.0.
Does the LPC812M101FDH16FP support in-application programming (IAP)?
Yes, the LPC812M101FDH16FP supports Flash In-Application Programming (IAP) via its on-chip 8 kB ROM API, which includes verified IAP routines for erasing and writing flash sectors without halting execution. This capability is documented in Section 7.4 of the LPC81xM objective data sheet and enables field firmware updates while maintaining real-time control - a core feature of the LPC812M101FDH16FP's design.
How many USART interfaces does the LPC812M101FDH16FP have, and are they all accessible in TSSOP16?
The LPC812M101FDH16FP integrates three USART interfaces (USART0, USART1, USART2), and all are fully accessible in the TSSOP16 package via the switch matrix. Unlike some variants, USART2 is explicitly supported on LPC812M101FDH16FP per Table 2 of the ordering information - enabling simultaneous UART communication with multiple peripherals without multiplexing or external logic.
What is the role of the switch matrix (SWM) in the LPC812M101FDH16FP?
The switch matrix (SWM) in the LPC812M101FDH16FP dynamically routes movable peripheral functions - including USART, SPI, I²C, SCT, and clock outputs - to any GPIO pin except VDD/VSS. This eliminates fixed peripheral pin constraints, allowing designers to optimize PCB layout and reuse firmware across variants. The LPC812M101FDH16FP's SWM is central to its flexibility, as confirmed in Section 7.9 of the official data sheet.
Can the LPC812M101FDH16FP wake up from Deep power-down mode, and how?
Yes, the LPC812M101FDH16FP can wake up from Deep power-down mode exclusively via the PIO0_4 pin, which functions as WAKEUP. A LOW-going pulse of at least 50 ns on this pin triggers wake-up - and the pin must not be assigned any movable function to preserve this capability. External pull-up is required for stable Deep power-down entry, as specified in Table 3 footnote [6] of the LPC812M101FDH16FP data sheet.
LPC812M101FDH16FP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Series:
- LPC81xM
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+
- Core Size:
- 32-Bit Single-Core
- Speed:
- 30MHz
- Connectivity:
- I2C, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, POR, PWM, WDT
- Number of I/O:
- 14
- Program Memory Size:
- 16KB (16K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 4K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- -
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC812M101FDH16FP FAQ
1.How can I place an order for LPC812M101FDH16FP through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC812M101FDH16FP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC812M101FDH16FP reliable?
The price and inventory of LPC812M101FDH16FP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC812M101FDH16FP is usually 5 days.
3.What payment methods are accepted for LPC812M101FDH16FP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC812M101FDH16FP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC812M101FDH16FP?
LPC812M101FDH16FP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC812M101FDH16FP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC812M101FDH16FP?
For technical support, including LPC812M101FDH16FP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC812M101FDH16FP requirements.
6.How does Aetrix verify that LPC812M101FDH16FP is sourced from the original manufacturer or authorized distributors?
All LPC812M101FDH16FP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC812M101FDH16FP meets industry standards.
7.What is the process for return or replacement of LPC812M101FDH16FP?
All LPC812M101FDH16FP units undergo pre-shipment inspection (PSI). If there is an issue with LPC812M101FDH16FP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC812M101FDH16FP part is unused and in its original packaging.
Return procedure for LPC812M101FDH16FP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC812M101FDH16FP Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

