NXP Semiconductors LPC812M101JDH20J
- Part No.:
- LPC812M101JDH20J
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 20-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
LPC812M101JDH20J.pdf
- Description:
- IC MCU 32BIT 16KB FLASH 20TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LPC812M101JDH20J from NXP Semiconductors is a 32-bit ARM Cortex-M0+ microcontroller operating at up to 30 MHz, featuring 16 kB flash, 4 kB SRAM, and 18 GPIO pins. It integrates a state-configurable timer/PWM (SCTimer), multi-rate timer (MRT), self-wake-up timer (WKT), CRC engine, and a comparator - deployed in lighting control, motor drive, and climate management systems.
For engineers reviewing the LPC812M101JDH20J datasheet, LPC812M101JDH20J pinout, LPC812M101JDH20J application, or LPC812M101JDH20J equivalent, key selection considerations include its TSSOP20 package with 20-pin layout, switch-matrix–enabled peripheral routing (USART0/1/2, SPI0/1, I2C0), 5 V-tolerant GPIO, and Deep power-down wake-up capability via PIO0_4.
Technical Context
The LPC812M101JDH20J implements an ARM Cortex-M0+ core with single-cycle I/O, NVIC, SysTick, and Micro Trace Buffer (MTB) for real-time debugging. Its clock system combines a 12 MHz ±1.5% internal RC oscillator, crystal oscillator (1–25 MHz), PLL, and programmable watchdog oscillator (9.4 kHz–2.3 MHz) to support flexible low-power operation.
Peripheral routing is managed by a hardware switch matrix enabling dynamic assignment of USART, SPI, I2C, SCTimer, and comparator functions to any non-power GPIO pin (PIO0_0 to PIO0_17). Fixed functions - including SWDIO/SWCLK, RESET, WAKEUP, XTALIN/XTALOUT, and VDDCMP - are mapped to specific pins per TSSOP20 layout, with true open-drain I2C support on PIO0_10/PIO0_11.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M0+, 30 MHz max - enables deterministic real-time control with <10 µs interrupt latency. |
| Memory | 16 kB flash / 4 kB SRAM - supports firmware updates via IAP/ISP and retains critical variables during low-power sleep. |
| GPIO | 18 pins with configurable pull-up/down, glitch filter, input inverter, and 20 mA sink/source - simplifies interface to sensors, LEDs, and discrete logic without external buffers. |
| Timers | SCTimer/PWM (input capture/match), MRT (4 fixed-rate interrupts), WKT (IRC- or LP-oscillator–clocked) - enables precise motor commutation, LED dimming, and periodic wake-up from Deep power-down. |
| Serial Interfaces | 3 USARTs, 2 SPIs, 1 I2C-bus - all assignable via switch matrix; I2C supports Fast-mode Plus when routed to PIO0_10/PIO0_11. |
| Power Modes | Sleep, Deep-sleep, Power-down, Deep power-down - Deep power-down draws <1 µA and wakes via PIO0_4 pulse or timer event. |
| Operating Range | −40 °C to 105 °C - qualified for industrial motor drives and climate control environments. |
Pinout & Package
TSSOP20 package: 20-pin, 4.4 mm body width, 0.65 mm pitch, lead-free, RoHS-compliant surface-mount device with exposed thermal pad (not electrically connected).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (PIO0_17) | General-purpose I/O | 5 V tolerant; configurable as input/output with pull-up/down, glitch filter, and inverter - usable for sensor polling or status indication. |
| 2 (PIO0_14) | General-purpose I/O | 5 V tolerant; supports movable functions (e.g., U1_TXD, SPI1_MOSI) via switch matrix - enables flexible peripheral routing. |
| 3 (PIO0_13) | General-purpose I/O | 5 V tolerant; default GPIO; can be assigned SCTimer inputs/outputs or I2C SDA/SCL - expands timing and communication options. |
| 4 (PIO0_0/ACMP_I1/TDO) | Multi-function pin | Fixed comparator input 1 or JTAG Test Data Out; GPIO disabled when ACMP_I1 or TDO active - preserves analog sensing or debug access. |
| 5 (PIO0_12) | ISP entry pin (v4C+) | LOW during reset triggers ISP command handler - enables field firmware recovery without dedicated programmer. |
| 6 (PIO0_6/VDDCMP) | Analog reference | VDDCMP provides alternate comparator reference voltage - allows ratiometric measurements independent of supply variation. |
| 7 (RESET/PIO0_5) | Reset input / GPIO | Active-low reset with 50 ns pulse width; doubles as GPIO if external reset not required - reduces BOM count in space-constrained designs. |
| 8 (PIO0_7) | General-purpose I/O | 5 V tolerant; supports high-current output (20 mA source) - directly drives LEDs or small relays. |
| 9 (PIO0_4/WAKEUP/TRST) | Wake-up trigger | LOW pulse wakes chip from Deep power-down; also serves as JTAG TRST - enables ultra-low-power remote sensor wake-up. |
| 10 (VSS) | Ground | Primary digital ground reference - must be low-impedance connection to minimize noise in ADC/comparator operation. |
| 11 (SWCLK/PIO0_3/TCK) | Debug clock | Serial Wire Clock input; enabled by default - provides standard SWD debug interface with minimal pin overhead. |
| 12 (VDD) | Supply | 3.3 V nominal supply; decoupling capacitor required near pin to stabilize core and analog domains. |
| 13 (SWDIO/PIO0_2/TMS) | Debug I/O | Serial Wire Debug bidirectional data line; default function enables programming and real-time trace - eliminates need for full JTAG connector. |
| 14 (PIO0_8/XTALIN) | Oscillator input | Crystal oscillator input (1–25 MHz); 1.95 V max input voltage - requires external crystal or clock source for precision timing. |
| 15 (PIO0_11) | I2C SDA (open-drain) | True open-drain; supports I2C Fast-mode Plus with external pull-up - ensures bus compliance and noise immunity in multi-node systems. |
| 16 (PIO0_9/XTALOUT) | Oscillator output | Crystal oscillator output; drives external crystal in parallel-resonant mode - completes clock generation circuit with minimal external parts. |
| 17 (PIO0_10) | I2C SCL (open-drain) | True open-drain; matches PIO0_11 for full I2C bus implementation - avoids signal integrity issues in mixed-speed I2C networks. |
| 18 (PIO0_1/ACMP_I2/CLKIN/TDI) | Comparator input / clock | Fixed comparator input 2 or external clock input; also JTAG TDI in boundary scan - supports analog monitoring or synchronous system clocking. |
| 19 (PIO0_16) | General-purpose I/O | 5 V tolerant; assignable to USART2 or SCTimer outputs - extends serial connectivity or PWM channel count. |
| 20 (PIO0_15) | General-purpose I/O | 5 V tolerant; supports pattern-match interrupt generation on boolean logic - enables hardware-accelerated event detection without CPU load. |
Key Features
| Feature | Design Value |
|---|---|
| Switch Matrix Peripheral Routing | Assigns USART, SPI, I2C, SCTimer, and comparator functions to any non-power GPIO pin - eliminates fixed-peripheral pin conflicts and reduces PCB layer count. |
| Deep Power-Down Wake-Up | Sub-1 µA retention current with wake-up via PIO0_4 pulse or WKT timeout - extends battery life in wireless sensor nodes beyond 10 years. |
| High-Current GPIO Drivers | 20 mA source on four pins and 20 mA sink on two true open-drain pins - directly interfaces with LEDs, buzzers, and optocouplers without external drivers. |
| Pattern-Match Interrupt Engine | Boolean logic evaluation across eight GPIO inputs - detects complex state transitions (e.g., encoder quadrature, button combos) in hardware, freeing CPU cycles. |
| On-Chip ROM API | 8 kB ROM with ISP/IAP, USART/I2C drivers, and power profile APIs - accelerates development and ensures consistent low-level peripheral control across firmware versions. |
Applications
| Lighting Control | Motor Drive |
|---|---|
Use Scenario: Smart LED driver board with dimming, color mixing, and thermal foldback. IC Role / Device Role / Timing Role: Main controller executing PWM timing via SCTimer, reading ambient light/temperature sensors, and communicating via I2C to RGB LED drivers. Use Value: 18 GPIO + switch matrix enables direct connection to 3-channel PWM outputs, I2C bus, and analog sensor inputs - reducing component count by 4 discrete ICs. | Use Scenario: Brushless DC (BLDC) fan controller with hall-effect commutation and speed regulation. IC Role / Device Role / Timing Role: Real-time commutation sequencer using SCTimer match/capture on hall sensor inputs and 3-phase PWM outputs. Use Value: SCTimer's input capture and output compare on same pins eliminates external logic, while 30 MHz core ensures <2 µs timing resolution for 30k RPM motors. |
| Climate Sensor Hub | Fire/Security Panel |
Use Scenario: Battery-powered HVAC node measuring temperature, humidity, CO₂, and airflow. IC Role / Device Role / Timing Role: Low-power coordinator sampling sensors via GPIO/ADC (external), managing UART-to-gateway comms, and waking every 30 s via WKT. Use Value: Deep power-down mode with 1 µA current and PIO0_4 wake-up extends CR2032 battery life to >5 years - eliminating maintenance cycles. | Use Scenario: Zone-monitoring panel with smoke/heat detectors, door contacts, and alarm siren. IC Role / Device Role / Timing Role: Fault-tolerant supervisor validating sensor states, driving audible/visual alarms, and reporting via RS-485 (USART2 + external transceiver). Use Value: Windowed Watchdog Timer (WWDT) and Brownout Detect ensure fail-safe shutdown during power anomalies - meeting EN54-4 compliance requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC812M101JD20 | SO20 package (7.5 mm width), 18 GPIO, identical flash/SRAM/peripherals - lacks PIO0_14/PIO0_15/PIO0_16/PIO0_17 pins. | Preferred for through-hole prototyping or legacy SOIC footprints; lower pin density limits peripheral routing flexibility. | Select when SO20 footprint is mandated and fewer GPIOs suffice; verify PCB layout accommodates wider body. |
| LPC824M201JDH20 | Enhanced variant: 32 kB flash, 8 kB SRAM, additional USART and I2C, same TSSOP20 package and pinout - software-compatible with LPC812M101JDH20J. | Suitable for feature-rich upgrades requiring larger code space or dual I2C buses (e.g., sensor fusion + display interface). | Choose for future-proofing where firmware growth is expected; no PCB change needed due to pin compatibility. |
Compared with LPC812M101JDH20J, LPC812M101JD20 offers reduced I/O count in a larger SOIC package, while LPC824M201JDH20 delivers scalable memory and peripherals within the same TSSOP20 footprint - enabling cost-optimized or feature-expanded design paths without layout rework.
Availability
LPC812M101JDH20J is available at Aetrix Electronics and suitable for lighting control, motor drive, and climate sensor hub applications requiring stable component supply, long-term industrial availability, and RoHS-compliant packaging.
Supply support for LPC812M101JDH20J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with over 40 years of microcontroller innovation.
The LPC800 series targets cost-sensitive, low-power embedded applications demanding high peripheral flexibility and rapid time-to-market - exemplified by the LPC812M101JDH20J's switch matrix architecture and integrated ROM APIs.
FAQ
What is the maximum operating frequency of the LPC812M101JDH20J?
The LPC812M101JDH20J operates at a maximum CPU frequency of 30 MHz using its ARM Cortex-M0+ core. This speed is achievable with the internal 12 MHz RC oscillator (trimmed to ±1.5%), external crystal (1–25 MHz), or PLL - all supported in the LPC812M101JDH20J's clock generation system without requiring external high-frequency components.
Does the LPC812M101JDH20J support in-system programming (ISP)?
Yes, the LPC812M101JDH20J supports ISP via its on-chip 8 kB ROM bootloader. Entry is triggered by a LOW level on PIO0_12 during reset (for chip revision 4C and later) or PIO0_1 (for revisions 1A/2A), using USART0 for communication. The ROM API handles flash erase/write operations, eliminating the need for external programming hardware.
How many USART interfaces does the LPC812M101JDH20J have, and how are they configured?
The LPC812M101JDH20J integrates three USART interfaces (USART0, USART1, USART2), all assignable to any GPIO pin via the hardware switch matrix. Each supports asynchronous/synchronous modes, RTS/CTS flow control, and clock output - with pin functions like U0_TXD, U1_RXD, and U2_SCLK defined in the movable function table of the datasheet.
What power-saving modes are available on the LPC812M101JDH20J?
The LPC812M101JDH20J offers four low-power modes: Sleep (CPU stopped, peripherals active), Deep-sleep (SRAM retained, clocks gated), Power-down (SRAM retained, regulators active), and Deep power-down (SRAM lost, <1 µA current). Wake-up sources include PIO0_4 pulse, WKT timeout, and activity on USART/SPI/I2C peripherals - all configurable in the PMU block.
Can the LPC812M101JDH20J's GPIO pins drive LEDs directly?
Yes, the LPC812M101JDH20J features high-current GPIO drivers: four pins support 20 mA source output and two true open-drain pins support 20 mA sink - sufficient to drive standard 20 mA LEDs without external transistors. Current limiting resistors must still be used, and pin assignments should avoid conflicting with fixed functions like SWD or XTAL.
LPC812M101JDH20J Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 20-TSSOP (0.173", 4.40mm Width)
- Series:
- LPC81xM
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+
- Core Size:
- 32-Bit Single-Core
- Speed:
- 30MHz
- Connectivity:
- I2C, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, POR, PWM, WDT
- Number of I/O:
- 18
- Program Memory Size:
- 16KB (16K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 4K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- -
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC812M101JDH20J FAQ
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6.How does Aetrix verify that LPC812M101JDH20J is sourced from the original manufacturer or authorized distributors?
All LPC812M101JDH20J products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC812M101JDH20J meets industry standards.
7.What is the process for return or replacement of LPC812M101JDH20J?
All LPC812M101JDH20J units undergo pre-shipment inspection (PSI). If there is an issue with LPC812M101JDH20J, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC812M101JDH20J part is unused and in its original packaging.
Return procedure for LPC812M101JDH20J:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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