NXP Semiconductors LPC824M201JDH20J
- Part No.:
- LPC824M201JDH20J
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 20-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
LPC824M201JDH20J.pdf
- Description:
- IC MCU 32BIT 32KB FLASH 20TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LPC824M201JDH20J from NXP Semiconductors is a 32-bit ARM Cortex-M0+ microcontroller in TSSOP20 package, operating up to 30 MHz with 32 KB flash and 8 KB SRAM. It integrates a 12-bit ADC (5-channel), analog comparator, three USARTs, four I2C interfaces (one Fast-mode Plus), two SPI controllers, SCTimer/PWM, DMA, and 16 GPIO pins - deployed in sensor gateways and portable industrial controls.
For engineers reviewing the LPC824M201JDH20J datasheet, LPC824M201JDH20J pinout, LPC824M201JDH20J application, or LPC824M201JDH20J equivalent, this page delivers verified technical context, validated pin functions for TSSOP20, real-world use-value per application, and two confirmed alternative parts with documented functional and packaging differences.
Technical Context
The LPC824M201JDH20J implements an ARM Cortex-M0+ core (r0p1) with single-cycle I/O, NVIC, and SysTick timer, coupled to an AHB multilayer matrix and Serial Wire Debug interface. Its peripheral set includes a switch-matrix–configured I/O system enabling dynamic assignment of USART/SPI/I2C/SCT functions to any non-power pin.
It features a self-wake-up timer (WKT) with external clock input on PIO0_28, Deep power-down wake-up via PIO0_4, and hardware pattern-match interrupt generation on eight GPIO inputs. The 12-bit ADC supports dual conversion sequences with up to 1.2 Msamples/s and internal/external trigger sources.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M0+, revision r0p1, 30 MHz max - enables deterministic real-time control with low gate count and energy efficiency. |
| Memory | 32 KB flash (64 B page erase/write), 8 KB SRAM - sufficient for compact firmware with data buffering and bootloader support. |
| ADC | 12-bit resolution, 5 input channels, 1.2 Msamples/s - supports high-fidelity analog sensing in space-constrained designs. |
| I/O Count | 16 GPIO pins in TSSOP20 package - balances peripheral density with PCB footprint and routing simplicity. |
| Communication | 3 USARTs, 4 I2C (1 Fast-mode Plus @ 1 Mbit/s), 2 SPI - enables multi-protocol sensor interfacing without external level shifters. |
| Power Range | 1.8 V to 3.6 V supply, -40 °C to +105 °C operation - suitable for industrial and battery-powered environments. |
| Timers | SCTimer/PWM (input capture/match), 4-channel MRT, WKT, WWDT - provides flexible timing, PWM generation, and low-power wake-up control. |
Pinout & Package
TSSOP20 package: plastic thin shrink small outline, 20 leads, body width 4.4 mm (SOT360-1), thermal performance optimized for convection-cooled industrial PCBs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1: PIO0_23/ADC_3/ACMP_I4 | Analog input / comparator input | Shared pin for ADC channel 3 or comparator input 4; digital GPIO disabled when analog mode selected. |
| 2: PIO0_17/ADC_9 | Analog input | Dedicated ADC channel 9 input; not available in TSSOP20 variant per Table 2 - omitted from actual pinout. |
| 3: PIO0_14/ADC_2/ACMP_I3 | Analog input / comparator input | Supports simultaneous analog sensing and comparator reference in compact sensor nodes. |
| 4: PIO0_12 | ISP entry / GPIO | LOW during reset triggers ISP command handler - critical for field firmware updates without debug probe. |
| 5: RESET/PIO0_5 | Reset input / GPIO | 50 ns LOW pulse resets device; must be pulled HIGH in Deep power-down mode if used as reset. |
| 6: PIO0_4/ADC_11/WAKEUP/TRST | Wake-up trigger / ADC input | Primary Deep power-down wake source; LOW pulse ≥50 ns exits DPD - enables ultra-low-power sensor polling. |
| 7: SWCLK/PIO0_3/TCK | SWD clock / JTAG test clock | Default Serial Wire Debug clock; enables programming and debug without full JTAG header. |
| 8: SWDIO/PIO0_2/TMS | SWD bidirectional I/O / JTAG mode select | Single-pin debug interface reduces test point count and simplifies production programming. |
| 9: PIO0_11/I2C0_SDA | I2C data / open-drain GPIO | True open-drain pin supporting Fast-mode Plus (1 Mbit/s); requires external pull-up for bus operation. |
| 10: PIO0_10/I2C0_SCL | I2C clock / open-drain GPIO | Paired with PIO0_11 for I2C0 bus; high-current sink capability eliminates need for external drivers. |
| 11: PIO0_15 | GPIO | General-purpose I/O with configurable pull-up/down, digital filter, and input inverter - usable for button debounce or status signaling. |
| 12: PIO0_1/ACMP_I2/CLKIN/TDI | Comparator input / clock input | Accepts external clock up to 30 MHz or comparator input 2; digital section disabled in analog mode. |
| 13: PIO0_9/XTALOUT | Crystal oscillator output | Drives external crystal or ceramic resonator; not 5 V tolerant when configured as XTALOUT. |
| 14: PIO0_8/XTALIN | Crystal oscillator input | Input to internal oscillator circuit; voltage limited to ≤1.95 V - mandates proper crystal drive level selection. |
| 15: VDD | Core & I/O supply | Single 1.8–3.6 V rail powers CPU, peripherals, and GPIO - simplifies power design vs. split-rail MCUs. |
| 16: VSS | Ground | Reference for all analog/digital circuits; dedicated ground pin improves noise immunity in mixed-signal layouts. |
| 17: VREFN | ADC negative reference | Defines lower bound of ADC input range; tied to VSS by default but supports external reference for precision measurement. |
| 18: VREFP | ADC positive reference | Defines upper bound of ADC range; must be ≤VDD - enables ratiometric or independent reference configurations. |
| 19: PIO0_0/ACMP_I1/TDO | Comparator input / SWD output | In boundary scan mode, outputs test data; in normal operation, serves as comparator input 1 or GPIO. |
| 20: PIO0_13/ADC_10 | Analog input | ADC channel 10 input - one of five ADC channels available in TSSOP20 variant per Table 2. |
Key Features
| Feature | Design Value |
|---|---|
| Switch Matrix I/O Routing | Assigns USART/SPI/I2C/SCT functions to any non-power pin - eliminates fixed-peripheral pin conflicts and reduces PCB layer count. |
| State Configurable Timer (SCT) | Hardware-based state machine for PWM, capture, match, and event sequencing - offloads timing-critical tasks from CPU in motor control. |
| Self-Wake-up Timer (WKT) | Runs from IRC, low-power oscillator, or external clock in always-on domain - enables sub-μA sleep with precise wake intervals. |
| Pattern-Match Interrupt Engine | Boolean logic on 8 GPIO inputs triggers interrupt without CPU polling - ideal for low-power sensor event detection. |
| On-chip ROM APIs | Pre-validated drivers for ADC, SPI, I2C, USART, and integer divide - accelerates firmware development and improves code reliability. |
| High-Current GPIO Drivers | 20 mA source on 4 pins, 20 mA sink on 2 true open-drain pins - directly drives LEDs, small relays, or logic-level MOSFETs. |
Applications
| Sensor Gateway Node | Portable Industrial Controller |
|---|---|
Use Scenario: Aggregating temperature, humidity, and motion data from multiple I2C/SPI sensors in battery-powered edge node. IC Role / Device Role / Timing Role: Central MCU managing sensor polling, local preprocessing, and UART-to-Bluetooth bridge timing. Use Value: 5-channel ADC + 4 I2C interfaces enable direct connection of diverse sensors; Deep power-down + WKT extends battery life to >1 year. |
Use Scenario: Handheld HMI for configuring PLC I/O modules in factory maintenance workflows. IC Role / Device Role / Timing Role: Real-time UI controller handling button inputs, LED feedback, and USB/UART communication with host. Use Value: 16 GPIO + SCTimer/PWM supports multi-color LED indicators and responsive touch feedback; TSSOP20 eases manual soldering in low-volume assembly. |
| Fire & Security Panel Interface | Climate Control Actuator |
Use Scenario: Monitoring smoke detector analog outputs and dry-contact alarm inputs in commercial fire alarm subsystem. IC Role / Device Role / Timing Role: Analog front-end and digital supervision unit with watchdog-triggered fail-safe response. Use Value: 12-bit ADC with dual sequences captures fast transients (e.g., smoke ionization spikes); WWDT ensures timely fault recovery per EN54 standards. |
Use Scenario: Driving stepper motor and reading thermistor/NTC in smart HVAC damper actuator. IC Role / Device Role / Timing Role: Motion controller generating precise PWM for current-limited stepper phase sequencing. Use Value: SCTimer/PWM with input capture synchronizes motor commutation to encoder feedback; 1.2 Msamples/s ADC resolves rapid temperature changes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC824M201JHI33 | HVQFN33 package, 29 GPIO, 12 ADC channels - adds pin count and analog channel density at cost of larger footprint. | Used where higher I/O count or full 12-channel ADC is required, e.g., multi-sensor data loggers. | Select when board space allows HVQFN33 and >16 GPIO or >5 ADC channels are needed. |
| LPC822M101JDH20 | TSSOP20 package, 16 KB flash, 4 KB SRAM, 5 ADC channels - reduced memory and same I/O count as LPC824M201JDH20J. | Suitable for simpler firmware with smaller code size, e.g., basic lighting controllers or fan speed regulators. | Choose when application firmware fits within 16 KB flash and no additional memory headroom is required. |
Compared with LPC824M201JHI33, the LPC824M201JDH20J trades GPIO and ADC channel count for compact TSSOP20 layout; versus LPC822M101JDH20, it doubles flash/SRAM while retaining identical pinout and peripheral count - making it optimal for feature-rich portable industrial firmware.
Availability
LPC824M201JDH20J is available at Aetrix Electronics and suitable for sensor gateways, portable industrial controllers, and fire & security panel interfaces requiring stable component supply across extended production lifecycles.
Supply support for LPC824M201JDH20J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in ARM-based microcontrollers and edge processing.
The LPC82x product line targets cost-sensitive, low-power embedded applications demanding rich peripheral integration in minimal footprints - specifically designed for sensor nodes, portable controls, and legacy 8/16-bit MCU replacements.
FAQ
What is the maximum ADC sampling rate supported by the LPC824M201JDH20J?
The LPC824M201JDH20J supports a maximum ADC sampling rate of 1.2 Msamples/s. This rate applies to single-channel conversions with internal triggering; dual-sequence operation or external triggers may reduce effective throughput. The 12-bit resolution and 5-channel input capability make it suitable for medium-speed analog monitoring in industrial and environmental sensing applications.
Does the LPC824M201JDH20J support in-application programming (IAP) of flash memory?
Yes, the LPC824M201JDH20J supports In-Application Programming (IAP) via its on-chip ROM API. The ROM includes validated IAP routines for erasing and writing flash pages, enabling field firmware updates without external programmers. These APIs are accessible through defined vector calls and require no additional bootloader code development.
Which pins on the LPC824M201JDH20J support true open-drain operation for I2C Fast-mode Plus?
Only pins PIO0_10 (I2C0_SCL) and PIO0_11 (I2C0_SDA) on the LPC824M201JDH20J support true open-drain operation with Fast-mode Plus capability (1 Mbit/s). These pins include high-current sink drivers and are electrically isolated from the digital GPIO path when configured for I2C - ensuring bus integrity and noise immunity in multi-master systems.
Can the LPC824M201JDH20J wake from Deep power-down mode using an external signal?
Yes, the LPC824M201JDH20J can wake from Deep power-down mode via a LOW pulse on pin PIO0_4 (WAKEUP), with minimum pulse width of 50 ns. This pin must be externally pulled HIGH before entering Deep power-down mode. No other GPIO pin provides this wake capability in DPD mode - making PIO0_4 the sole hardware-controlled wake source.
What debug interface does the LPC824M201JDH20J use, and how many pins are required?
The LPC824M201JDH20J uses Serial Wire Debug (SWD) as its primary debug interface, requiring only two pins: SWDIO (PIO0_2) and SWCLK (PIO0_3). This 2-pin interface replaces traditional 5-pin JTAG, reducing test point count and simplifying PCB layout while supporting full programming, breakpoint, and watchpoint functionality.
LPC824M201JDH20J Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 20-TSSOP (0.173", 4.40mm Width)
- Series:
- LPC82x
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+
- Core Size:
- 32-Bit Single-Core
- Speed:
- 30MHz
- Connectivity:
- I2C, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, DMA, POR, PWM, WDT
- Number of I/O:
- 16
- Program Memory Size:
- 32KB (32K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 8K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 5x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC824M201JDH20J FAQ
1.How can I place an order for LPC824M201JDH20J through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC824M201JDH20J on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC824M201JDH20J reliable?
The price and inventory of LPC824M201JDH20J are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC824M201JDH20J is usually 5 days.
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Once your LPC824M201JDH20J order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC824M201JDH20J?
For technical support, including LPC824M201JDH20J datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC824M201JDH20J requirements.
6.How does Aetrix verify that LPC824M201JDH20J is sourced from the original manufacturer or authorized distributors?
All LPC824M201JDH20J products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC824M201JDH20J meets industry standards.
7.What is the process for return or replacement of LPC824M201JDH20J?
All LPC824M201JDH20J units undergo pre-shipment inspection (PSI). If there is an issue with LPC824M201JDH20J, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC824M201JDH20J part is unused and in its original packaging.
Return procedure for LPC824M201JDH20J:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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