NXP Semiconductors LPC845M301JHI33E

Overview

LPC845M301JHI33E from NXP Semiconductors is a 32-bit Arm Cortex-M0+ microcontroller operating at up to 30 MHz, featuring 64 KB flash, 16 KB SRAM, one 12-bit ADC (12-channel, 1.2 Msps), two 10-bit DACs, and capacitive touch interface - deployed in compact HVQFN33 packages for space-constrained sensor gateways and portable control systems.

For engineers reviewing the LPC845M301JHI33E datasheet, LPC845M301JHI33E pinout, LPC845M301JHI33E application, or LPC845M301JHI33E equivalent, this page delivers verified package mapping, validated peripheral configuration, confirmed GPIO count (29 pins), real-world timing role in low-power wake-up systems, and direct alternative part comparisons with documented functional trade-offs.

Technical Context

The LPC845M301JHI33E implements an Arm Cortex-M0+ core (r0p1) with single-cycle I/O and nested vectored interrupt controller (NVIC), paired with a multilayer AHB matrix and Serial Wire Debug (SWD) interface supporting four breakpoints and two watchpoints. Its clock system integrates a factory-trimmed Free Running Oscillator (FRO) delivering ±1% accuracy across 0–70°C at 18/24/30 MHz, plus PLL support for full-speed CPU operation without external crystal dependency.

Peripheral routing uses a programmable switch matrix enabling flexible assignment of USART, SPI, I2C, SCTimer/PWM, and ADC functions to non-power pins. The device supports hardware-triggered DMA transfers across 25 channels with 13 trigger sources, and includes dedicated low-power domains for self-wake-up timer (WKT) and deep power-down mode - where only WAKEUP (PIO0_4) and RESET (PIO0_5) remain active for external wake events.

Key Specifications

Pinout & Package

HVQFN33 package: 5 mm × 5 mm body, 0.85 mm height, 33-terminal thermal-enhanced no-lead construction with exposed thermal pad (pin 33 = VSS). Pin 1 index located at top-left corner per JEDEC MO-220.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microcontroller applications.

Compared with LPC845M301JHI33E, LPC845M301JBD48 offers expanded I/O and dual DAC capability in a larger package, while LPC824M201JHI33 provides a scaled-down, cost-optimized alternative with identical HVQFN33 form factor but reduced memory and peripheral count - enabling tiered design reuse.

Availability

LPC845M301JHI33E is available at Aetrix Electronics and suitable for sensor gateways, portable wearables, and fire/security panels requiring stable component supply, long-term industrial lifecycle support, and RoHS-compliant HVQFN packaging.

Supply support for LPC845M301JHI33E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with over 50 years of innovation in microcontrollers and analog devices.

The LPC800 series - including LPC845M301JHI33E - was designed for cost-sensitive, space-constrained embedded applications demanding rich analog integration, low-power operation, and flexible I/O routing without sacrificing Arm Cortex-M performance.

FAQ

What is the maximum operating frequency of the LPC845M301JHI33E?

The LPC845M301JHI33E operates at a maximum CPU frequency of 30 MHz, achieved via its internal Free Running Oscillator (FRO) or PLL. The FRO is factory-trimmed to ±1% accuracy across 0–70°C and supports selectable outputs of 18 MHz, 24 MHz, or 30 MHz - all usable as system clock sources without external crystal dependency. This enables deterministic real-time execution in resource-constrained applications.

How many GPIO pins does the LPC845M301JHI33E provide in the HVQFN33 package?

The LPC845M301JHI33E provides 29 general-purpose I/O pins in the HVQFN33 package, as confirmed in Table 2 of the official datasheet. This count excludes power, ground, debug, and dedicated analog pins (e.g., VDDA, VREFP/N), and reflects only user-configurable digital I/O capable of pull-up/down, open-drain, and interrupt generation - sufficient for compact sensor node and wearable interface designs.

Does the LPC845M301JHI33E support both DAC outputs?

No, the LPC845M301JHI33E supports only DACOUT_0 (on PIO0_17) - DACOUT_1 (PIO0_29) is not available in the HVQFN33 package, as indicated by dash entries in Table 4's HVQFN33 column for that pin. This is a package-specific limitation, not a silicon restriction; the same LPC845 die in LQFP64/LQFP48/HVQFN48 variants includes both DAC outputs.

What debug interface does the LPC845M301JHI33E use, and which pins are required?

The LPC845M301JHI33E uses Serial Wire Debug (SWD) as its primary debug interface, requiring two pins: SWDIO (PIO0_2, Pin 7) and SWCLK (PIO0_3, Pin 6). These pins are enabled by default at reset and support full programming, real-time debugging, breakpoints, and watchpoints - eliminating need for JTAG cabling while maintaining compatibility with standard ARM debug tools like SEGGER J-Link and CMSIS-DAP.

Can the LPC845M301JHI33E wake from deep power-down mode using external signals?

Yes, the LPC845M301JHI33E can wake from deep power-down mode via two dedicated pins: PIO0_4/WAKEUP (Pin 4) and PIO0_5/RESET (Pin 3). Both pins retain functionality in deep power-down and respond to low-going pulses (≥50 ns for WAKEUP, ≥20 ns for RESET). No other GPIOs remain active in this mode - confirming strict reliance on these two pins for external wake events in ultra-low-power deployments.