NXP Semiconductors LPC845M301JHI33K
- Part No.:
- LPC845M301JHI33K
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
LPC845M301JHI33K.pdf
- Description:
- IC MCU 32BIT 64KB FLASH 32HVQFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,717
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC845M301JHI33K from NXP Semiconductors is a 32-bit Arm Cortex-M0+ microcontroller operating at up to 30 MHz, featuring 64 KB flash, 16 KB SRAM, one 12-bit ADC (12-channel, 1.2 Msamples/s), two 10-bit DACs, and capacitive touch interface - deployed in compact HVQFN33 packaging for space-constrained sensor gateways and portable control systems.
For engineers reviewing the LPC845M301JHI33K datasheet, LPC845M301JHI33K pinout, LPC845M301JHI33K application, or LPC845M301JHI33K equivalent, this page delivers verified package mapping, validated peripheral routing constraints, confirmed low-power wake-up behavior on PIO0_4, and precise GPIO count (29 pins) with switch-matrix flexibility - all critical for PCB layout and firmware bring-up in industrial edge nodes.
Technical Context
The LPC845M301JHI33K integrates an Arm Cortex-M0+ core with single-cycle I/O and nested vectored interrupt controller (NVIC), coupled with a multilayer AHB matrix enabling concurrent peripheral access. Its clock system combines a factory-trimmed Free Running Oscillator (±1% over 0–70°C), PLL for CPU scaling, and external crystal support (1–25 MHz).
Peripheral routing is managed by a programmable switch matrix that maps movable functions (USART, SPI, I2C, SCTimer, ADC triggers) to any non-power/non-ground pin - while fixed-function pins (e.g., PIO0_2/TMS, PIO0_3/TCK, PIO0_5/RESET) retain debug and reset roles. The device supports deep power-down mode with wake-up via PIO0_4 (WAKEUP), RESET, or self-wake-up timer (WKT) clocked from FRO or external source.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M0+ @ up to 30 MHz - enables deterministic real-time control with low latency interrupt response and single-cycle GPIO access. |
| Memory | 64 KB flash / 16 KB SRAM - sufficient for bootloader, application code, and dual-bank data buffering in sensor fusion or motor commutation tasks. |
| Analog Peripherals | 12-bit ADC (12 ch, 1.2 Msps) + two 10-bit DACs - supports high-fidelity analog signal acquisition and closed-loop actuator control without external converters. |
| Digital Interfaces | 5 USARTs, 4 I2C (1 Fast-mode Plus), 2 SPI - provides flexible serial connectivity for multi-sensor networks and host communication in wearables or lighting controllers. |
| Power & Temp | 1.8–3.6 V supply, -40°C to +105°C operation - suitable for industrial environments and battery-powered portables requiring extended thermal margin. |
| Package | HVQFN33 (5 × 5 × 0.85 mm) - ultra-compact footprint with 29 GPIOs, optimized for space-limited PCBs in gaming controllers or climate sensors. |
| Low-Power Modes | Sleep, deep-sleep, power-down, deep power-down - enables sub-μA standby current with configurable wake-up sources including PIO0_4 and WKT. |
Pinout & Package
HVQFN33 package: 5 mm × 5 mm body, 0.85 mm height, 33-terminal thermal-enhanced no-lead construction with exposed thermal pad (pin 33 = VSS). Pin 1 index located at top-left corner per JEDEC MO-220.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PIO0_0 / ACMP_I1 / TDO | Analog comparator input / JTAG test output | Default GPIO; selectable as comparator input or boundary scan output - not used for primary I/O in default configuration. |
| PIO0_2 / SWDIO / TMS | Serial Wire Debug I/O / JTAG mode select | Enabled for SWD by default; essential for programming and real-time debugging without full JTAG overhead. |
| PIO0_3 / SWCLK / TCK | Serial Wire Clock / JTAG clock | Primary debug clock input; required for SWD-based firmware updates and trace capture via Micro Trace Buffer (MTB). |
| PIO0_4 / ADC_11 / TRST / WAKEUP | ADC input / test reset / deep power-down wake trigger | Hardware-asserted wake source: LOW pulse ≥50 ns exits deep power-down - must remain unassigned to movable functions if used. |
| PIO0_5 / RESET | External reset input | Active-low asynchronous reset with 20–50 ns pulse requirement; also wakes from deep power-down when externally pulled LOW. |
| PIO0_29 / DACOUT_1 | 10-bit DAC output channel 1 | Analog voltage output (0–VDDA) for precision biasing or waveform generation; requires external filtering for clean signal reconstruction. |
| VDDA | Analog supply | Must be decoupled separately from digital VDD; powers ADC, DACs, comparator, and XTAL circuitry - noise-sensitive domain. |
| VSS (Pin 33) | Ground reference | Exposed thermal pad tied to PCB ground plane - mandatory for thermal dissipation and EMI suppression in HVQFN33 layout. |
Key Features
| Feature | Design Value |
|---|---|
| Switch Matrix I/O Routing | Enables dynamic assignment of USART/SPI/I2C/SCTimer functions to any non-power pin - eliminates fixed peripheral pin conflicts and simplifies PCB routing. |
| Capacitive Touch Interface | Supports up to 9 X/Y sensor channels (CAPT_X0–X8, CAPT_YL/YH) - enables touch-button or slider implementation without external ICs in wearables or HMI panels. |
| Self-Wake-Up Timer (WKT) | Operates from FRO (1.5–30 MHz), external clock, or low-power oscillator - allows precise timed wake-up from deep power-down with sub-second resolution. |
| High-Current GPIO Drivers | Four pins support 20 mA source, two true open-drain pins support 20 mA sink - directly drive LEDs, small relays, or logic-level MOSFETs without buffer stages. |
| FRO Clock Accuracy | Factory-trimmed ±1% over 0–70°C - eliminates need for external crystal in cost-sensitive applications where timing tolerance permits. |
Applications
| Smart Sensor Node | Portable Lighting Controller |
|---|---|
|
Use Scenario: Compact environmental sensor node measuring temperature, humidity, and air quality with BLE or LoRaWAN uplink. IC Role / Device Role / Timing Role: Central MCU managing ADC sampling, capacitive touch for user interface, and UART-to-radio bridging. Use Value: 29 GPIOs in HVQFN33 enable direct sensor interfacing; 12-bit ADC ensures accurate analog readings; low-power modes extend battery life to >1 year. |
Use Scenario: RGB LED driver board for architectural lighting with dimming, color mixing, and touch-based scene selection. IC Role / Device Role / Timing Role: Real-time PWM generator (SCTimer/PWM) controlling three independent LED channels plus capacitive touch decoder. Use Value: Two 10-bit DACs provide smooth analog dimming references; switch matrix routes I2C to ambient light sensor and touch controller simultaneously. |
| Gaming Peripheral | Industrial Climate Monitor |
|
Use Scenario: Wireless gamepad with motion sensing, button matrix, haptic feedback, and USB HID emulation via UART bridge. IC Role / Device Role / Timing Role: Low-latency input processor handling GPIO scan, ADC for analog stick, and USART for host communication. Use Value: 30 MHz Cortex-M0+ ensures sub-2 ms button-to-host latency; 5 USARTs support simultaneous debug, radio, and HID interfaces. |
Use Scenario: DIN-rail mounted HVAC sensor unit monitoring CO₂, temperature, and humidity in commercial buildings. IC Role / Device Role / Timing Role: Industrial-grade data concentrator with RS-485 (via USART), I2C sensor bus, and watchdog-protected operation. Use Value: -40°C to +105°C rating ensures reliability in unconditioned enclosures; windowed watchdog (WWDT) prevents firmware lockup in mission-critical deployments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC845M301JBD48 | LQFP48 package (7×7 mm), 42 GPIOs, same 64 KB flash/16 KB SRAM, includes full capacitive touch support (2× CAPT_Y) | Requires larger PCB area but offers more GPIOs and full Y-axis touch channel support - better for complex HMI designs | Select when additional I/O or full capacitive touch matrix (X+Y) is needed; not pin-compatible due to different package and pin count |
| LPC824M201JHI33 | HVQFN33 package, 32 KB flash, 8 KB SRAM, no DACs, no capacitive touch, only 2 USARTs and 2 I2C interfaces | Lower-cost option for basic control tasks without analog output or touch - suited for simple relay controllers or fan speed regulators | Select when budget constraints outweigh need for DACs/touch; shares HVQFN33 footprint but differs in peripheral set and memory size |
Compared with LPC845M301JHI33K, the LPC845M301JBD48 expands I/O count and touch capability at the cost of board space, while the LPC824M201JHI33 reduces feature set and memory to lower BOM cost - making LPC845M301JHI33K the optimal balance of analog integration, compactness, and peripheral richness for mid-tier embedded applications.
Availability
LPC845M301JHI33K is available at Aetrix Electronics and suitable for sensor gateways, portable lighting controllers, and industrial climate monitors requiring stable component supply across automotive-qualified temperature ranges and long-term production cycles.
Supply support for LPC845M301JHI33K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in Arm-based microcontrollers and edge processing.
The LPC84x product line was designed for cost-sensitive, space-constrained embedded applications demanding rich analog integration, low-power operation, and flexible I/O routing - targeting sensor nodes, wearables, and smart peripherals.
FAQ
What is the maximum operating frequency of the LPC845M301JHI33K?
The LPC845M301JHI33K operates at a maximum CPU frequency of 30 MHz, achieved using its internal Free Running Oscillator (FRO) or PLL. This frequency is fully supported across the specified industrial temperature range (-40°C to +105°C) and 1.8–3.6 V supply voltage, enabling deterministic real-time performance in time-critical control loops.
How many GPIO pins does the LPC845M301JHI33K provide in its HVQFN33 package?
The LPC845M301JHI33K provides 29 general-purpose I/O pins in the HVQFN33 package, as confirmed in Table 2 of the official datasheet. These include dedicated analog inputs (ADC_0–ADC_11), DAC outputs (DACOUT_0/DACOUT_1), and capacitive touch channels (CAPT_X0–X8, CAPT_YL/YH), all accessible through the switch matrix.
Does the LPC845M301JHI33K support capacitive touch sensing?
Yes, the LPC845M301JHI33K includes a dedicated Capacitive Touch Interface supporting up to nine X-axis channels (CAPT_X0–X8) and two Y-axis channels (CAPT_YL/YH). In the HVQFN33 package, CAPT_YH and CAPT_YL are available on pins PIO1_8 and PIO1_9, enabling robust touch-button or slider implementations without external components.
What are the wake-up sources from deep power-down mode on the LPC845M301JHI33K?
The LPC845M301JHI33K supports wake-up from deep power-down mode via three hardware sources: the WAKEUP pin (PIO0_4), the RESET pin (PIO0_5), and the Self-Wake-Up Timer (WKT). The WAKEUP pin requires a LOW-going pulse ≥50 ns, while the WKT can be clocked from FRO, external source, or low-power oscillator - all verified in Section 7.2 of the datasheet.
Is the LPC845M301JHI33K pin-compatible with other LPC84x variants in HVQFN33?
No, the LPC845M301JHI33K is not pin-compatible with LPC844M201JHI33 in HVQFN33. Although both share the same package, the LPC844 variant lacks DAC outputs (PIO0_29/DACOUT_1 and PIO0_17/DACOUT_0) and capacitive touch functionality, and has only 8 KB SRAM versus 16 KB - resulting in different functional pin assignments and register configurations.
LPC845M301JHI33K Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 32-VFQFN Exposed Pad
- Series:
- LPC84x
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+
- Core Size:
- 32-Bit
- Speed:
- 30MHz
- Connectivity:
- I2C, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, DMA, POR, PWM, WDT
- Number of I/O:
- 29
- Program Memory Size:
- 64KB (64K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 16K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 12x12b SAR; D/A 1x10b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC845M301JHI33K FAQ
1.How can I place an order for LPC845M301JHI33K through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC845M301JHI33K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC845M301JHI33K reliable?
The price and inventory of LPC845M301JHI33K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC845M301JHI33K is usually 5 days.
3.What payment methods are accepted for LPC845M301JHI33K?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC845M301JHI33K transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC845M301JHI33K?
LPC845M301JHI33K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC845M301JHI33K order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC845M301JHI33K?
For technical support, including LPC845M301JHI33K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC845M301JHI33K requirements.
6.How does Aetrix verify that LPC845M301JHI33K is sourced from the original manufacturer or authorized distributors?
All LPC845M301JHI33K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC845M301JHI33K meets industry standards.
7.What is the process for return or replacement of LPC845M301JHI33K?
All LPC845M301JHI33K units undergo pre-shipment inspection (PSI). If there is an issue with LPC845M301JHI33K, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC845M301JHI33K part is unused and in its original packaging.
Return procedure for LPC845M301JHI33K:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC845M301JHI33K Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

