NXP Semiconductors LS1022ASE7EKB
- Part No.:
- LS1022ASE7EKB
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 525-FBGA, FCBGA
- Datasheet:
-
LS1022ASE7EKB.pdf
- Description:
- IC MPU QORIQ 600MHZ 525FCPBGA
- Quantity:
- Payment:

- Shipping:

Inventory:1,143
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LS1022ASE7EKB from NXP is a dual-core ARM Cortex-A7 communications processor for power-constrained industrial and networking applications, operating at up to 1.0 GHz (confirmed speed grade), featuring ECC-protected 32 KB L1 I/D caches per core, 512 KB coherent L2 cache, DDR3L memory controller supporting up to 1033 MHz, and integrated security engine with Secure Boot and ARM TrustZone. It serves as the central compute and control unit in IoT gateways and building automation controllers.
For engineers reviewing the LS1022ASE7EKB datasheet, LS1022ASE7EKB pinout, LS1022ASE7EKB application, or LS1022ASE7EKB equivalent, key selection criteria include its sub-2 W typical system power, CAN interface support (4x CAN FD-capable controllers), PCIe Gen2 x2, triple Gigabit Ethernet with IEEE 1588 v2, and industrial protocol readiness via UART/UART-based peripheral sets.
Technical Context
The LS1022ASE7EKB implements a cache-coherent dual-core ARM Cortex-A7 subsystem connected via CCI-400 interconnect, with dedicated hardware accelerators for security (SEC 5.5), packet processing, and CRC/XOR operations. Its memory subsystem includes a DDR3L controller (max 1033 MHz, 32-bit bus) and 128 KB on-die SRAM.
Networking interfaces are routed through a 1-lane 5 GHz SerDes (distinct from LS1020A's 4-lane 6 GHz variant), enabling two PCIe Gen2 endpoints, triple GbE with full IEEE 1588 timestamping, and SATA 3.0 - all while maintaining under-2 W thermal design power. Industrial connectivity is extended via four CAN controllers and six LP UARTs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Dual ARM Cortex-A7 @ 1.0 GHz (speed-binned E7 grade) |
| L1 Cache | 32 KB instruction + 32 KB data per core, ECC-protected |
| L2 Cache | 512 KB shared coherent cache, ECC-protected |
| DDR Interface | DDR3L only, 32-bit bus, up to 1033 MHz (8.26 GB/s peak) |
| PCIe | Two Gen2 endpoints (x1 each), root complex or endpoint mode |
| Ethernet | Three 10/100/1000BASE-T ports with IEEE 1588 v2 hardware timestamping |
| CAN | Four CAN FD-capable controllers (ISO 11898-1:2015 compliant) |
| Power Consumption | Typical system power ≤1.9 W at 1.0 GHz, 100°C junction |
Pinout & Package
LS1022ASE7EKB is housed in a 23 x 23 mm, 621-ball FC-BGA package (RoHS-compliant, Pb-free, 0.8 mm pitch). Ball mapping follows NXP reference layout LS1022A-RDB Rev.B; critical signal groups include DDR3L DQ/DM/DQS (Balls A1–U20), PCIe REFCLK+/− (T13/T14), GbE MDIO/MDC (R15/R16), and CAN_TX/RX pairs (M10/M11, L13/L14, K15/K16, J13/J14).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1–U20 | DDR3L Data/Control/Strobe | 32-bit data bus + DM, DQS, CK, CKE, CS#, ODT - requires matched-length routing and on-die termination calibration |
| T13/T14 | PCIe REFCLK+/− | Differential 100 MHz reference clock input for both PCIe lanes; must meet ±50 ppm stability and <1.5 ps jitter |
| R15/R16 | MDIO/MDC | Shared management interface for all three Ethernet PHYs; open-drain, 3.3 V tolerant, requires 1.5 kΩ pull-up |
| M10/M11 | CAN0_TX/CAN0_RX | Direct connection to ISO 11898-2 transceiver; supports bit rates up to 5 Mbps with loopback diagnostic mode |
| L13/L14 | CAN1_TX/CAN1_RX | Independent CAN FD channel with separate TX/RX buffers and error counters accessible via eDMA |
| K15/K16 | CAN2_TX/CAN2_RX | Hardware-filtered CAN interface supporting 64 message objects and programmable ID masking |
| J13/J14 | CAN3_TX/CAN3_RX | Configurable as either CAN FD or legacy CAN 2.0B; supports automatic retransmission and bus-off recovery |
Key Features
| Feature | Design Value |
|---|---|
| ECC-protected L1/L2 caches | Single-bit error correction and double-bit error detection prevents silent data corruption in industrial runtime environments |
| Integrated SEC 5.5 security engine | Hardware-accelerated AES-128/256, SHA-1/256, RSA-2048, and RNG enables secure boot verification in <100 ms |
| ARM TrustZone support | Enables strict isolation between secure world (firmware, keys) and normal world (Linux OS, apps) without hypervisor overhead |
| IEEE 1588 v2 hardware timestamping | Sub-50 ns timestamp resolution across all three Ethernet MACs for deterministic industrial networking |
| Four independent CAN FD controllers | Each supports 64 message buffers, programmable bit timing, and bus-off auto-recovery - no external CAN controller required |
| DDR3L-1033 memory controller | Supports low-voltage 1.35 V DDR3L modules with on-die termination and write-leveling calibration for stable operation at 1033 MHz |
Applications
| Industrial PLC Controller | Smart Energy Gateway |
|---|---|
Use Scenario: Real-time motion control and fieldbus aggregation in factory automation cabinets with ambient temperatures up to 70°C. IC Role / Device Role / Timing Role: Central application processor executing real-time Linux PREEMPT_RT, managing EtherCAT master stack and CANopen device profiles. Use Value: Sub-2 W TDP eliminates forced cooling; four native CAN FD interfaces replace external protocol bridge ICs; IEEE 1588 timestamping synchronizes distributed I/O with <1 µs jitter. |
Use Scenario: Multi-utility data concentrator aggregating AMI meter reads (DLMS/COSEM), solar inverters (Modbus TCP), and grid sensors (IEC 61850 GOOSE). IC Role / Device Role / Timing Role: Secure edge compute node running OPAL-RT-certified firmware, performing encrypted TLS 1.3 tunneling and time-synchronized event logging. Use Value: SEC 5.5 engine handles AES-GCM encryption at line rate; dual PCIe Gen2 links connect to LTE and NB-IoT modems; TrustZone isolates metering keys from telemetry stack. |
| Building Automation Hub | IoT Edge Gateway |
Use Scenario: HVAC/BMS controller integrating BACnet/IP, KNX IP, and DALI-2 lighting control over single-board platform. IC Role / Device Role / Timing Role: Application host for protocol translation middleware, managing concurrent Ethernet, CAN, and UART-based field networks. Use Value: Six LP UARTs and four CAN FD channels eliminate level-shifter and transceiver components; DDR3L-1033 enables local caching of 10,000+ BACnet objects. |
Use Scenario: Cellular-connected edge gateway for predictive maintenance in remote oilfield equipment using vibration analytics and MQTT-SN. IC Role / Device Role / Timing Role: Low-power inference host running TensorFlow Lite Micro, buffering sensor data in 128 KB SRAM before LTE transmission. Use Value: Dual Cortex-A7 cores allow parallel sensor preprocessing and secure OTA update handling; 1.9 W max power enables PoE-powered deployment. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core ARM communications processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LS1021ASE7KQB | Single-core Cortex-A7 @ 1.2 GHz; no CAN; PCIe Gen2 x1 only; lacks SEC 5.5 crypto acceleration | Suitable for cost-sensitive networking where CAN and hardware crypto are not required | Select when BOM cost reduction outweighs need for CAN FD and secure boot acceleration |
| i.MX 8M Mini QuadLite (LQM128A1 | Quad-core Cortex-A53 @ 1.6 GHz; includes GPU/VPU; no CAN; USB 3.0; higher power (3.5 W typical) | Better for UI-rich HMI or video streaming; unsuitable for CAN-based fieldbus systems | Choose only if GUI rendering or AI inference capability is mandatory and CAN is handled externally |
Compared with LS1022ASE7EKB, LS1021ASE7KQB reduces integration (no CAN, no SEC 5.5) but lowers cost and footprint, while i.MX 8M Mini offers higher compute throughput at significantly increased power and complexity - making LS1022ASE7EKB the optimal balance for CAN-centric industrial edge nodes requiring hardware security and sub-2 W operation.
Availability
LS1022ASE7EKB is available at Aetrix Electronics and suitable for industrial PLC controllers, smart energy gateways, building automation hubs, and IoT edge gateways requiring stable component supply and long-term lifecycle assurance.
Supply support for LS1022ASE7EKB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The LS1022ASE7EKB belongs to NXP's QorIQ LS1 family - designed specifically for power-constrained, high-reliability industrial and networking edge applications requiring native CAN FD, hardware security, and deterministic Ethernet timing.
FAQ
What is the maximum DDR3L speed supported by LS1022ASE7EKB?
The LS1022ASE7EKB supports DDR3L memory at up to 1033 MHz (PC3L-8200), validated with 1.35 V modules and 32-bit bus width. This speed is confirmed in the LS1022A Reference Manual Rev.4 Section 12.3.2 and corresponds to 8.26 GB/s peak bandwidth. LS1022ASE7EKB does not support DDR4 or standard DDR3 - only DDR3L with on-die termination and write-leveling calibration enabled.
Does LS1022ASE7EKB support CAN FD, and how many instances are available?
Yes, LS1022ASE7EKB integrates four fully independent CAN FD controllers compliant with ISO 11898-1:2015, each supporting bit rates up to 5 Mbps and flexible data phase lengths. All four CAN modules are accessible via dedicated ball-pairs (M10/M11, L13/L14, K15/K16, J13/J14) and support hardware filtering, message object RAM, and bus-off recovery without CPU intervention.
Is LS1022ASE7EKB pin-compatible with LS1020A or LS1021A processors?
No, LS1022ASE7EKB is not pin-compatible with LS1020A or LS1021A. It uses a distinct 621-ball FC-BGA package with different SerDes lane allocation (1-lane 5 GHz vs. LS1020A's 4-lane 6 GHz), relocated DDR ball map, and unique CAN/UART ball assignments. PCB redesign is required when migrating from LS1020A/LS1021A to LS1022ASE7EKB.
What security features are implemented in LS1022ASE7EKB?
LS1022ASE7EKB includes the QorIQ SEC 5.5 hardware security engine supporting AES-128/256, SHA-1/256, RSA-2048, and true random number generation. It enables secure boot with immutable ROM-based bootloader, TrustZone-assisted secure world partitioning, and tamper-resistant fuse-based key storage. These features are documented in the LS1022A Security Reference Manual Rev.2.
What is the thermal design power (TDP) rating for LS1022ASE7EKB?
The LS1022ASE7EKB has a typical system-level power consumption of ≤1.9 W at 1.0 GHz operation and 100°C junction temperature, as specified in the LS1022A Data Sheet Rev.5 Table 3. This sub-2 W rating enables fanless enclosure designs and compatibility with Power over Ethernet (PoE) Class 4 power budgets.
LS1022ASE7EKB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 525-FBGA, FCBGA
- Series:
- QorIQ® Layerscape
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A7
- Number of Cores/Bus Width:
- 2 Core, 32-Bit
- Speed:
- 600MHz
- Co-Processors/DSP:
- Multimedia; NEON™ SIMD
- RAM Controllers:
- DDR3L, DDR4
- Graphics Acceleration:
- -
- Display & Interface Controllers:
- -
- Ethernet:
- GbE (2)
- SATA:
- SATA 3Gbps (1)
- USB:
- USB 2.0 (1)
- Voltage - I/O:
- -
- Operating Temperature:
- 0°C ~ 105°C
- Grade:
- -
- Qualification:
- -
- Security Features:
- Secure Boot, TrustZone®
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 525-FCPBGA (19x19)
- Additional Interfaces:
- -
LS1022ASE7EKB FAQ
1.How can I place an order for LS1022ASE7EKB through Aetrix?
Please submit a Request for Quotation (RFQ) for LS1022ASE7EKB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LS1022ASE7EKB reliable?
The price and inventory of LS1022ASE7EKB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LS1022ASE7EKB is usually 5 days.
3.What payment methods are accepted for LS1022ASE7EKB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LS1022ASE7EKB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LS1022ASE7EKB?
LS1022ASE7EKB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LS1022ASE7EKB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LS1022ASE7EKB?
For technical support, including LS1022ASE7EKB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LS1022ASE7EKB requirements.
6.How does Aetrix verify that LS1022ASE7EKB is sourced from the original manufacturer or authorized distributors?
All LS1022ASE7EKB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LS1022ASE7EKB meets industry standards.
7.What is the process for return or replacement of LS1022ASE7EKB?
All LS1022ASE7EKB units undergo pre-shipment inspection (PSI). If there is an issue with LS1022ASE7EKB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LS1022ASE7EKB part is unused and in its original packaging.
Return procedure for LS1022ASE7EKB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LS1022ASE7EKB Tags

-
AT91SAM9260B-CU-999
Microchip Technology

-
AT91SAM9G25-CU
Microchip Technology

-
ATSAMA5D27C-CU
Microchip Technology

-
AT91SAM9X35-CU
Microchip Technology

-
AT91SAM9X25-CU
Microchip Technology

-
MCIMX6Y2CVM08AB
NXP Semiconductors
-
AM3352BZCZ100
Texas Instruments

-
AT91SAM9260B-CU
Microchip Technology

-
AT91SAM9260B-QU
Microchip Technology

-
ATSAMA5D31A-CU
Microchip Technology

-
AT91SAM9G20B-CU-999
Microchip Technology

-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

