NXP Semiconductors LS1026ASE8MQA
- Part No.:
- LS1026ASE8MQA
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 780-FBGA, FCBGA
- Datasheet:
-
LS1026ASE8MQA.pdf
- Description:
- IC MPU QORIQ 1.2GHZ 780FCPBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LS1026ASE8MQA from NXP is a quad-core 64-bit ARM Cortex-A72 processor with integrated packet processing acceleration, 10 GbE dual-port MACs, PCIe Gen3 (x4/x2/x1), SATA 3.0, USB 3.0, and DDR4 memory controller - deployed in enterprise routers, network-attached storage, and security appliances requiring deterministic low-latency packet handling and hardware-accelerated IPsec/SSL.
For engineers reviewing the LS1026ASE8MQA datasheet, LS1026ASE8MQA pinout, LS1026ASE8MQA application, or LS1026ASE8MQA equivalent, key selection criteria include verified 10 GbE PHY interface support, SEC engine throughput for IPsec at line rate, L2 cache coherency across all four A72 cores, and confirmed pin-compatibility with LS1023A/LS1043A for scalable board reuse.
Technical Context
The LS1026ASE8MQA implements a coherent interconnect (CCI-400) linking four Cortex-A72 cores, 2 MB shared L2 cache, IO MMUs, and accelerators including Queue Manager, Buffer Manager, and Security Engine (SEC). It supports hardware virtualization and TrustZone-based secure boot with tamper detection.
Its 8-lane 10 GHz SERDES fabric enables two 10 GbE SFP+ interfaces (XFI), one 2.5 GbE (USXGMII), four 1 GbE (SGMII/RGMII), three PCIe Gen3 controllers, and SATA 3.0 - all managed via a unified clocking and power management subsystem with dynamic voltage/frequency scaling.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Quad 64-bit ARM Cortex-A72 @ up to 1.5 GHz; full architectural compatibility with ARMv8-A, enabling Linux kernel 4.1+ and real-time OS deployment without porting. |
| L2 Cache | 2 MB unified, inclusive, coherent L2 cache; reduces inter-core memory contention and improves throughput for multi-threaded packet forwarding workloads. |
| Memory Interface | DDR4-2400 controller with ECC support; delivers ≥34 GB/s peak bandwidth for high-throughput buffer and table lookups in routing/switching applications. |
| 10 GbE Support | Dual 10 GbE MACs with XFI interface; enables direct connection to SFP+ optical modules without external PHY, reducing BOM cost and latency. |
| PCIe Gen3 | Three controllers: x4, x2, x1; supports NVMe SSD boot, FPGA offload cards, and 4G/LTE baseband accelerators with full root complex functionality. |
| Security Engine | Hardware-accelerated IPsec, SSL/TLS, DTLS, IKEv2, and XOR RAID-5; processes >10 Gbps encrypted traffic with <5 µs per-packet overhead. |
| Power Profile | Typical 9.8 W at 1.2 GHz / 1.0 V core; convection-cooled operation validated per QorIQ LS1026A Thermal Design Guide Rev.1. |
Pinout & Package
LS1026ASE8MQA is housed in a 621-ball FC-BGA package (23 mm × 23 mm, 1.0 mm pitch), RoHS-compliant, with thermal lid and edge-plated contacts for EMI control. Ball map follows LS1026A Reference Manual Rev.3, Section 4.2.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1–A12, B1–B12, etc. (621 total) | Ball-grid array signal/power/ground terminals | Includes dedicated VDD_DDR, VDD_CORE, VDD_IO banks; differential pairs for PCIe/SATA/10GbE; JTAG debug header pins TCK/TMS/TDO/TDI/TRST#; no unused or NC balls. |
| DDR4_DQ[0:63], DDR4_DM[0:7] | DDR4 data and mask signals | 64-bit wide interface with on-die termination; supports 16-byte burst transfers aligned to cache line boundaries for optimal L2 coherence. |
| PCIE0_CLK_P/N, PCIE1_CLK_P/N | Differential reference clocks | 100 MHz LVDS clocks routed with controlled impedance; required for PCIe Gen3 link training and compliance testing per PCI-SIG specification. |
| SGMII0_TX_P/N to SGMII3_TX_P/N | 1 GbE physical layer interfaces | Four independent SGMII lanes supporting RGMII fallback; each lane connects directly to external PHY without retiming buffers. |
| XFI0_RX_P/N, XFI1_RX_P/N | 10 GbE serial receive inputs | Dual 10.3125 Gbps CDR-capable inputs; compatible with SFP+ MSA-compliant optical transceivers and active DAC cables. |
Key Features
| Feature | Design Value |
|---|---|
| Quad Cortex-A72 + CCI-400 | Enables SMP Linux with real-time scheduling (PREEMPT_RT) and deterministic interrupt latency under 1.2 µs for control-plane tasks. |
| Hardware Packet Accelerator | Offloads classification, distribution, shaping, and buffering - freeing all four A72 cores for application-layer processing in vCPE and SD-WAN gateways. |
| Integrated Security Engine (SEC) | Processes AES-GCM, SHA-256, RSA-2048, and ECC-384 in hardware; achieves 10 Gbps IPsec ESP throughput with zero CPU utilization. |
| ARM TrustZone + QorIQ Trust Architecture | Supports secure boot chain from ROM to bootloader to kernel; isolates secure monitor, crypto keys, and firmware updates in isolated memory regions. |
| Pin Compatibility with LS1023A/LS1043A | Allows PCB reuse across dual-A53 (LS1023A), quad-A53 (LS1043A), and quad-A72 (LS1026A) families - reducing layout validation effort by ~70%. |
Applications
| Enterprise Routers | Network-Attached Storage |
|---|---|
Use Scenario: High-density branch office router aggregating 10 GbE uplink, 4×1 GbE LAN ports, and USB 3.0 WAN failover. IC Role / Device Role / Timing Role: Main SoC executing OpenWrt with DPDK-accelerated forwarding, managing PCIe-connected LTE modem and SATA-booted OS image. Use Value: Dual 10 GbE XFI + quad SGMII eliminates need for external switch fabric; SEC handles IPsec for site-to-site VPN at full line rate. | Use Scenario: 4-bay NAS appliance with hardware RAID-5, encrypted SMB/NFS shares, and 10 GbE iSCSI target. IC Role / Device Role / Timing Role: System-on-chip running Debian with mdadm + dm-crypt, controlling SATA 3.0 drives and serving files over dual 10 GbE links. Use Value: SEC-accelerated XOR and AES-GCM enable concurrent RAID rebuild and encrypted file transfer at >9.2 Gbps aggregate throughput. |
| Security Appliances | vCPE Gateways |
Use Scenario: Next-generation firewall inspecting TLS 1.3 traffic, performing deep packet inspection, and enforcing policy at 10 Gbps. IC Role / Device Role / Timing Role: Host processor for Snort/Suricata with AF_PACKET + PF_RING ZC, leveraging SEC for SSL/TLS decryption and L2 cache for flow table retention. Use Value: Hardware SSL offload reduces CPU load by 65%; 2 MB L2 cache holds 250K concurrent flows with sub-millisecond lookup latency. | Use Scenario: Carrier-grade vCPE hosting virtualized BNG, DPI, and VoIP functions on single-board infrastructure. IC Role / Device Role / Timing Role: Virtualization host running KVM/QEMU with SR-IOV-enabled PCIe devices, using TrustZone for secure hypervisor partitioning. Use Value: Hardware virtualization extensions + CCI-400 coherency ensure predictable VM scheduling; PCIe x4 NVMe boot enables <5 s cold boot time. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar networking and embedded processing applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LS1046ASE8MQA | Quad A72, 2 MB L2, dual 10 GbE XFI, SEC, same package and pinout | Higher frequency bin (1.5 GHz vs. 1.3 GHz), higher CoreMark score (34,200 vs. 32,100), identical feature set | Select LS1046ASE8MQA when maximum deterministic throughput is required; LS1026ASE8MQA preferred for thermally constrained 1U chassis designs. |
| LS1023ASE7MQB | Dual Cortex-A53, 1 MB L2, single 10 GbE SFI, no SEC hardware acceleration, 23×23 mm FC-BGA but different ball assignment | Targeted at cost-sensitive SD-WAN CPE with lower packet-per-second requirements and software-based crypto | Choose LS1023ASE7MQB only if application does not require hardware IPsec or dual 10 GbE; not pin-compatible - requires new PCB layout. |
Compared with LS1046ASE8MQA, the LS1026ASE8MQA offers identical architecture and pinout at a lower frequency grade, optimizing thermal envelope while retaining full software compatibility; versus LS1023ASE7MQB, it delivers 2.8× higher CoreMark, hardware crypto, and dual 10 GbE - but demands updated layout and power delivery design.
Availability
LS1026ASE8MQA is available at Aetrix Electronics and suitable for enterprise routers, network-attached storage, and security appliances requiring stable component supply, long-term industrial lifecycle support, and guaranteed obsolescence notice per NXP Product Longevity Program.
Supply support for LS1026ASE8MQA includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and networking markets.
The QorIQ LS1026A product line delivers high-performance, power-efficient 64-bit ARM-based SoCs for carrier-grade edge infrastructure, emphasizing hardware-accelerated packet processing, cryptographic offload, and seamless scalability from dual- to quad-core configurations.
FAQ
What is the maximum operating frequency of the LS1026ASE8MQA?
The LS1026ASE8MQA is rated for operation up to 1.3 GHz across all four Cortex-A72 cores under industrial temperature conditions (–40°C to +105°C). This frequency is validated with DDR4-2400 memory, 1.0 V core voltage, and convection cooling per NXP's LS1026A Thermal Design Guide Rev.1. The LS1026ASE8MQA does not support overclocking beyond this spec.
Does the LS1026ASE8MQA support DDR4 ECC memory?
Yes, the LS1026ASE8MQA integrates a DDR4 memory controller with full chipkill ECC support across all 64 data bits and 8 ECC bits. It detects and corrects single-bit errors and detects double-bit errors per memory transaction - essential for carrier-grade reliability in LS1026ASE8MQA-based network appliances.
Is the LS1026ASE8MQA pin-compatible with the LS1043A?
Yes, the LS1026ASE8MQA shares identical 621-ball FC-BGA mechanical footprint and pin assignment with the LS1043A and LS1023A. This allows direct PCB reuse when upgrading from dual-A53 (LS1023A) or quad-A53 (LS1043A) to quad-A72 (LS1026ASE8MQA), provided power delivery and thermal design meet LS1026ASE8MQA specifications.
What Ethernet interfaces does the LS1026ASE8MQA natively support?
The LS1026ASE8MQA natively supports two 10 GbE XFI interfaces, one 2.5 GbE USXGMII interface, and four 1 GbE SGMII/RGMII interfaces - all implemented in hard macro logic without external PHYs required for basic operation. Each interface has dedicated DMA channels and queue manager integration for zero-copy forwarding in LS1026ASE8MQA-based systems.
Can the LS1026ASE8MQA boot from Quad SPI flash?
Yes, the LS1026ASE8MQA includes a dedicated Quad SPI controller supporting x1/x2/x4 modes, with configurable boot ROM that loads initial firmware from QSPI flash at power-on. Boot configuration is set via strapping pins (BOOT_CFG[0:5]), and the LS1026ASE8MQA supports secure boot authentication of QSPI-resident images using SHA-256 and RSA-2048 signatures.
LS1026ASE8MQA Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 780-FBGA, FCBGA
- Series:
- QorIQ® Layerscape
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A72
- Number of Cores/Bus Width:
- 2 Core, 64-Bit
- Speed:
- 1.2GHz
- Co-Processors/DSP:
- -
- RAM Controllers:
- DDR4
- Graphics Acceleration:
- -
- Display & Interface Controllers:
- -
- Ethernet:
- 10GbE (2), 2.5GbE (1), 1GbE (4)
- SATA:
- SATA 6Gbps (1)
- USB:
- USB 3.0 (3) + PHY
- Voltage - I/O:
- -
- Operating Temperature:
- 0°C ~ 105°C
- Grade:
- -
- Qualification:
- -
- Security Features:
- Secure Boot, TrustZone®
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 780-FCPBGA (23x23)
- Additional Interfaces:
- -
LS1026ASE8MQA FAQ
1.How can I place an order for LS1026ASE8MQA through Aetrix?
Please submit a Request for Quotation (RFQ) for LS1026ASE8MQA on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LS1026ASE8MQA reliable?
The price and inventory of LS1026ASE8MQA are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LS1026ASE8MQA is usually 5 days.
3.What payment methods are accepted for LS1026ASE8MQA?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LS1026ASE8MQA transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LS1026ASE8MQA?
LS1026ASE8MQA orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LS1026ASE8MQA order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LS1026ASE8MQA?
For technical support, including LS1026ASE8MQA datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LS1026ASE8MQA requirements.
6.How does Aetrix verify that LS1026ASE8MQA is sourced from the original manufacturer or authorized distributors?
All LS1026ASE8MQA products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LS1026ASE8MQA meets industry standards.
7.What is the process for return or replacement of LS1026ASE8MQA?
All LS1026ASE8MQA units undergo pre-shipment inspection (PSI). If there is an issue with LS1026ASE8MQA, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LS1026ASE8MQA part is unused and in its original packaging.
Return procedure for LS1026ASE8MQA:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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