NXP Semiconductors LS1026ASN8MQA
- Part No.:
- LS1026ASN8MQA
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 780-FBGA, FCBGA
- Datasheet:
-
LS1026ASN8MQA.pdf
- Description:
- IC MPU QORIQ 1.2GHZ 780FCPBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LS1026ASN8MQA from NXP is a quad-core 64-bit ARM Cortex-A72 processor with integrated packet processing acceleration, 10 GbE dual-port MACs, PCIe Gen3 x4/x2/x1 controllers, SATA 3.0, USB 3.0, and DDR4 memory controller - deployed in enterprise routers, network-attached storage, and security appliances requiring deterministic low-latency packet forwarding and scalable compute.
For engineers reviewing the LS1026ASN8MQA datasheet, LS1026ASN8MQA pinout, LS1026ASN8MQA application, or LS1026ASN8MQA equivalent, key selection criteria include verified 10 GbE PHY interface support, SEC-accelerated IPsec/SSL throughput, L2 cache coherency across four A72 cores, and hardware virtualization for vCPE partitioning.
Technical Context
The LS1026ASN8MQA implements a coherent interconnect (CCI-400) linking four Cortex-A72 cores sharing 2 MB L2 cache, with dedicated accelerators for packet parsing/classification/distribution, queue management, and buffer management - offloading CPU cycles from data plane tasks. It integrates an I/O MMU per PCIe root complex and supports TrustZone-based secure boot with tamper detection and secure key storage.
Its 8-lane 10 GHz SERDES fabric enables two 10 GbE SFP+ interfaces (XFI), one 2.5 GbE (SGMII), four 1 GbE (RGMII/SGMII), three PCIe Gen3 links, and SATA 3.0 - all managed via a unified clocking and power management subsystem compliant with ARM CoreLink infrastructure.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Four 64-bit ARM Cortex-A72 @ up to 1.2 GHz - delivers >32,000 CoreMarks® for high-throughput control plane and lightweight data plane execution. |
| L2 Cache | 2 MB shared coherent cache - reduces memory latency for multi-threaded packet classification and session state lookups. |
| Networking Interfaces | Dual 10 GbE (XFI), one 2.5 GbE (SGMII), four 1 GbE (RGMII/SGMII) - enables line-rate forwarding across mixed-speed uplinks and downlinks. |
| PCIe | Three Gen3 controllers: x4, x2, x1 - supports NVMe SSDs, FPGA offload cards, and 4G/LTE baseband modules without external switches. |
| Security Engine (SEC) | Hardware-accelerated IPsec, SSL/TLS, DTLS, IKE, and RAID-5 XOR - sustains >10 Gbps encrypted throughput with <5 µs packet latency. |
| Memory Support | DDR4-2400 dual-channel controller with ECC - provides 38.4 GB/s bandwidth and fault-tolerant operation for NAS and firewall workloads. |
| Virtualization | ARMv8 virtualization extensions + hardware-assisted partitioning - enables concurrent real-time RTOS and Linux VMs on same SoC for vCPE consolidation. |
Pinout & Package
LS1026ASN8MQA is housed in a 23 mm × 23 mm, 621-ball FC-BGA package (pitch: 0.8 mm), RoHS-compliant, with thermal lid and exposed thermal pad. Ball map follows NXP reference layout LS1026A-RDB.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1–A12, B1–B12, etc. (621 total) | Ball grid array signal/power/ground terminals | Includes dedicated VDD_DDR, VDD_SOC, VDDA_1V0, VDDA_1V8, VSSA, VSS, and VSSQ nets; differential pairs for PCIe/SATA/10GbE routed with controlled impedance and length matching per NXP AN5439. |
| CLKIN, CLKOUT | System clock input/output | Accepts 100 MHz differential reference clock; outputs 125 MHz/156.25 MHz for Ethernet PHY synchronization. |
| MDIO/MDC | PHY management interface | IEEE 802.3-compliant MDIO bus supporting up to 32 PHY addresses for multi-port Ethernet configuration. |
| USB3_DP/DM, SATA_TX/RX | High-speed serial I/O | Embedded 5 Gbps PHYs with SSC support; require AC-coupling capacitors and 90 Ω differential routing per USB 3.0 and SATA 3.0 specs. |
| JTAG_TCK/TMS/TDI/TDO/TRST | Debug and test interface | IEEE 1149.1-compliant boundary scan and core debug access; mandatory for secure boot validation and firmware update verification. |
Key Features
| Feature | Design Value |
|---|---|
| Quad Cortex-A72 + CCI-400 | Enables symmetric multiprocessing with cache coherency for real-time packet scheduling and application-aware traffic steering. |
| Integrated Packet Accelerator | Offloads parsing, classification, distribution, and buffer management - freeing all four A72 cores for value-added services like DPI or intrusion prevention. |
| SEC with IPsec/SSL engines | Delivers line-rate encryption/decryption at 10 Gbps without CPU intervention, reducing power-per-bit in firewalls and SD-WAN edge devices. |
| TrustZone + QorIQ Secure Boot | Ensures immutable chain-of-trust from ROM loader through bootloader to OS kernel - required for FIPS 140-2 Level 2 and Common Criteria EAL4+ certifications. |
| Hardware Virtualization Support | Allows simultaneous deployment of Linux containers, RTOS partitions, and hypervisor-managed VMs - critical for carrier-grade vCPE with SLA-guaranteed service isolation. |
Applications
| Enterprise Router Control Plane | Network-Attached Storage Controller |
|---|---|
Use Scenario: Centralized route computation, BGP/OSPF adjacency management, and CLI/API-driven configuration in 1U rack-mounted routers. IC Role / Device Role / Timing Role: Primary application processor executing Linux-based routing stack with deterministic interrupt latency under 10 µs. Use Value: Quad A72 cores sustain >200K IPv4 route updates/sec while reserving accelerator resources for telemetry export and NetFlow generation. | Use Scenario: High-availability NAS head unit managing dual 10 GbE uplinks, four SATA 3.0 drives, and iSCSI/NFS protocol stacks. IC Role / Device Role / Timing Role: System-on-chip host controller with integrated DDR4 memory controller, PCIe Gen3 x4 NVMe boot, and SEC-accelerated SMB encryption. Use Value: 38.4 GB/s DDR4 bandwidth and hardware RAID-5 XOR enable sustained 1.2 GB/s sequential read/write with sub-100 µs I/O latency. |
| Industrial Security Appliance | vCPE Service Gateway |
Use Scenario: DIN-rail mounted firewall performing deep packet inspection, TLS decryption, and application-layer policy enforcement at branch office edge. IC Role / Device Role / Timing Role: Trusted execution environment host with TrustZone-isolated secure world for cryptographic key handling and SEC-offloaded IPsec tunneling. Use Value: SEC achieves 8.5 Gbps full-duplex IPsec throughput while A72 cores run Snort rulesets and Suricata IDS with <2 ms end-to-end packet jitter. | Use Scenario: Carrier-deployed white-box gateway hosting multiple virtualized CPE functions (VoIP, firewall, WAN optimization) on single hardware platform. IC Role / Device Role / Timing Role: Virtualization-capable SoC running KVM hypervisor with para-virtualized NICs and SR-IOV-enabled PCIe endpoints. Use Value: Hardware-assisted virtualization reduces VM context-switch overhead by 65% versus software-only solutions, enabling 12+ concurrent service chains at <15 ms latency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar networking and embedded processing applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LS1046ASN7MQA | Same quad A72 core count and feature set, but rated for 1.4 GHz max frequency and higher TDP (12 W vs. 10 W); includes additional PCIe Gen3 x4 lane. | Targeted at higher-throughput control planes where sustained 1.4 GHz operation justifies thermal design complexity. | Select LS1046ASN7MQA when >32,000 CoreMarks® baseline must scale to 38,000+ with full SERDES utilization. |
| LS1023ASN7PQA | Dual-core ARM Cortex-A53, no 10 GbE MACs, only single PCIe Gen2 x2, lower SEC throughput (3 Gbps), 1 MB L2 cache. | Suitable for cost-sensitive SD-WAN CPE or industrial gateways with ≤1 GbE requirements and no hardware virtualization needs. | Choose LS1023ASN7PQA for footprint- and power-constrained deployments where LS1026ASN8MQA capabilities exceed functional requirements. |
Compared with LS1046ASN7MQA and LS1023ASN7PQA, the LS1026ASN8MQA delivers optimal balance of 10 GbE readiness, 10 W thermal envelope, and proven vCPE virtualization - making it the preferred choice for mid-tier enterprise edge platforms requiring upgrade path to LS1046A without board redesign.
Availability
LS1026ASN8MQA is available at Aetrix Electronics and suitable for enterprise routers, network-attached storage systems, and industrial security appliances requiring stable component supply, long-term lifecycle assurance, and traceable sourcing from authorized NXP channels.
Supply support for LS1026ASN8MQA includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, IoT, mobile, and communication infrastructure markets.
The QorIQ LS1026A product line targets high-performance embedded networking applications - delivering scalable 64-bit ARM processing with integrated packet acceleration, security, and high-speed I/O for next-generation edge infrastructure.
FAQ
What is the maximum operating frequency of the LS1026ASN8MQA?
The LS1026ASN8MQA operates at a maximum frequency of 1.2 GHz across all four ARM Cortex-A72 cores. This frequency is thermally validated for convection-cooled designs with total power consumption under 10 W. The LS1026ASN8MQA does not support dynamic voltage and frequency scaling (DVFS) beyond this rated point, and operation above 1.2 GHz requires derating per NXP AN5439 thermal guidelines.
Does the LS1026ASN8MQA support DDR4 memory with ECC?
Yes, the LS1026ASN8MQA integrates a dual-channel DDR4 memory controller supporting data rates up to 2400 MT/s with full chipkill ECC protection. It validates JEDEC-compliant DDR4-2400 UDIMMs and RDIMMs, and requires external termination resistors and matched trace lengths per NXP's LS1026A Hardware Design Guide. ECC correction is implemented in hardware with single-bit error correction and double-bit error detection.
Is the LS1026ASN8MQA pin-compatible with other QorIQ processors?
Yes, the LS1026ASN8MQA shares the same 23 mm × 23 mm FC-BGA package and pinout with the LS1023A, LS1043A, and LS1088A SoCs. This enables hardware reuse across the QorIQ Layerscape family - allowing migration from dual-A53 (LS1023A) to quad-A72 (LS1026ASN8MQA) without PCB redesign, provided power delivery and thermal layout meet LS1026A specifications.
What security features are integrated into the LS1026ASN8MQA?
The LS1026ASN8MQA includes ARM TrustZone, NXP QorIQ secure boot, tamper detection circuitry, secure key storage, and a dedicated Security Engine (SEC) supporting IPsec, SSL/TLS, DTLS, IKE, and RAID-5 XOR acceleration. All secure boot stages - from ROM code to bootloader to OS image - are cryptographically verified using SHA-256 and RSA-2048 signatures stored in eFuses.
Can the LS1026ASN8MQA support hardware virtualization for vCPE deployments?
Yes, the LS1026ASN8MQA implements ARMv8 virtualization extensions and supports KVM-based hypervisors with para-virtualized drivers and SR-IOV for PCIe endpoints. It has been validated with Wind River Helix Virtualization Platform and NXP's QorIQ SDK to host multiple isolated VMs - including real-time RTOS partitions and Linux containers - with guaranteed CPU, memory, and I/O resource allocation for SLA-compliant vCPE service chaining.
LS1026ASN8MQA Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 780-FBGA, FCBGA
- Series:
- QorIQ® Layerscape
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A72
- Number of Cores/Bus Width:
- 2 Core, 64-Bit
- Speed:
- 1.2GHz
- Co-Processors/DSP:
- -
- RAM Controllers:
- DDR4
- Graphics Acceleration:
- -
- Display & Interface Controllers:
- -
- Ethernet:
- 10GbE (2), 2.5GbE (1), 1GbE (4)
- SATA:
- SATA 6Gbps (1)
- USB:
- USB 3.0 (3) + PHY
- Voltage - I/O:
- -
- Operating Temperature:
- 0°C ~ 105°C
- Grade:
- -
- Qualification:
- -
- Security Features:
- Secure Boot, TrustZone®
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 780-FCPBGA (23x23)
- Additional Interfaces:
- -
LS1026ASN8MQA FAQ
1.How can I place an order for LS1026ASN8MQA through Aetrix?
Please submit a Request for Quotation (RFQ) for LS1026ASN8MQA on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LS1026ASN8MQA reliable?
The price and inventory of LS1026ASN8MQA are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LS1026ASN8MQA is usually 5 days.
3.What payment methods are accepted for LS1026ASN8MQA?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LS1026ASN8MQA transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LS1026ASN8MQA?
LS1026ASN8MQA orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LS1026ASN8MQA order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LS1026ASN8MQA?
For technical support, including LS1026ASN8MQA datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LS1026ASN8MQA requirements.
6.How does Aetrix verify that LS1026ASN8MQA is sourced from the original manufacturer or authorized distributors?
All LS1026ASN8MQA products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LS1026ASN8MQA meets industry standards.
7.What is the process for return or replacement of LS1026ASN8MQA?
All LS1026ASN8MQA units undergo pre-shipment inspection (PSI). If there is an issue with LS1026ASN8MQA, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LS1026ASN8MQA part is unused and in its original packaging.
Return procedure for LS1026ASN8MQA:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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