NXP Semiconductors LS1026ASN8Q1A
- Part No.:
- LS1026ASN8Q1A
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 780-FBGA, FCBGA
- Datasheet:
-
LS1026ASN8Q1A.pdf
- Description:
- IC MPU QORIQ 1.6GHZ 780FCPBGA
- Quantity:
- Payment:

- Shipping:

Inventory:2,060
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Product details
Overview
LS1026ASN8Q1A from NXP is a quad-core 64-bit ARM Cortex-A72 processor with integrated packet processing acceleration, 10 GbE dual-port MACs, PCIe Gen3 x4/x2/x1 controllers, SATA 3.0, USB 3.0 with PHY, and DDR4 memory controller - deployed in enterprise routers, network-attached storage, and security appliances requiring deterministic low-latency packet handling.
For engineers reviewing the LS1026ASN8Q1A datasheet, LS1026ASN8Q1A pinout, LS1026ASN8Q1A application, or LS1026ASN8Q1A equivalent, key selection criteria include verified 10 GbE MAC timing compliance, SEC hardware acceleration for IPsec/SSL, TrustZone-enabled secure boot, and pin compatibility with LS1023A/LS1043A for scalable platform reuse.
Technical Context
The LS1026ASN8Q1A implements four coherent ARM Cortex-A72 cores backed by 2 MB shared L2 cache and CCI-400 interconnect, supporting 32-bit and 64-bit execution modes. It integrates a dedicated packet processing engine (PPE) with hardware queue manager, buffer manager, and classifier/distributor logic to offload forwarding-plane tasks from CPU cores.
Security is enforced via NXP's Security Engine (SEC) supporting AES-GCM, SHA-256, RSA-2048, IPsec ESP/AH, SSL/TLS record processing, and XOR acceleration for RAID 5. TrustZone and QorIQ trust architecture enable secure boot, tamper detection, and isolated debug access.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Quad 64-bit ARM Cortex-A72 @ up to 1.5 GHz - delivers >32,000 CoreMarks® for high-throughput control-plane processing |
| L2 Cache | 2 MB unified, shared, coherent - reduces memory bandwidth pressure and improves multi-threaded throughput |
| Networking Interfaces | Dual 10 GbE MAC + one 2.5 GbE MAC + four 1 GbE MAC - enables multi-rate linecard or vCPE gateway with hardware timestamping support |
| PCIe | Three controllers: x4, x2, x1 Gen3 - supports NVMe SSD, FPGA offload, or 10G SFP+ adapter without external switch |
| Security Engine | Hardware-accelerated IPsec, SSL/TLS, DTLS, IKEv2, AES-GCM, SHA-256 - sustains >10 Gbps encrypted throughput at <10 W total SoC power |
| Memory Interface | DDR4-2400 dual-channel with ECC - provides 38.4 GB/s peak bandwidth and fault-tolerant operation for industrial control applications |
| Trust Architecture | ARM TrustZone + NXP QorIQ secure boot & tamper detection - enforces chain-of-trust from ROM to OS, preventing unauthorized firmware loading |
Pinout & Package
LS1026ASN8Q1A is housed in a 23 mm × 23 mm, 621-ball FC-BGA package (RoHS-compliant, Pb-free). Ball pitch is 1.0 mm; package height is 2.31 mm max. Thermal pad on underside requires solder paste stencil design per NXP AN5097.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1–A10, B1–B10, etc. (621 total) | Ball grid array signal/power/ground balls | Includes dedicated VDD_DDR, VDD_SOC, VDD_IO banks with separate power sequencing requirements; critical clocks (REFCLK, DDR_CLK) require controlled impedance routing |
| DDR4_DQ[0:63], DDR4_DM[0:7] | DDR4 data and data mask signals | Supports 72-bit wide interface (64-bit data + 8-bit ECC); DQ/DQS skew must be ≤ ±15 ps for 2400 MT/s operation |
| PCIE0_RX[0:3], PCIE0_TX[0:3] | PCIe Gen3 differential lanes (x4) | Requires 85 Ω differential impedance; AC-coupling capacitors placed within 5 mm of SoC ball; reference clock routed as 100 MHz LVDS |
| SGMII0–SGMII4, XFI0–XFI1 | Multi-mode Ethernet physical layer interfaces | Configurable as SGMII (1 GbE), 2.5G SGMII, or XFI (10 GbE); each pair needs 100 Ω differential routing and internal termination enabled |
| USB3_DP0/DM0, USB3_DP1/DM1, USB3_DP2/DM2 | USB 3.0 SuperSpeed differential pairs | Integrated PHY eliminates need for external transceivers; requires 90 Ω differential impedance and strict length matching (<50 mil) |
Key Features
| Feature | Design Value |
|---|---|
| Packet Processing Engine (PPE) | Hardware classifier/distributor with 16K-entry flow table and dynamic buffer allocation - enables line-rate 10 GbE forwarding at <5 µs latency without CPU intervention |
| Security Engine (SEC) | Dedicated crypto accelerator supporting concurrent IPsec SA setup, TLS handshake offload, and RAID 5 XOR - frees ≥2 A72 cores for application-layer services |
| ARM TrustZone + QorIQ Trust Architecture | Hardware-enforced isolation between secure world (bootloader, key store) and normal world (Linux kernel, apps) - meets IEC 62443-3-3 SL2 requirements |
| Scalable Pin Compatibility | Identical ball map to LS1023A/LS1043A/LS1088A - allows PCB reuse across dual-A53 to octal-A53 to quad-A72 product families |
| DDR4 Memory Controller with ECC | Supports 64 GB max capacity, on-die ECC correction, and address parity - ensures data integrity in industrial control and telecom baseband applications |
Applications
| Enterprise Routers | Network-Attached Storage |
|---|---|
Use Scenario: High-density branch office router aggregating 10 GbE uplink, multiple 1 GbE LAN ports, and USB 3.0 WAN failover. IC Role / Device Role / Timing Role: Main application processor executing Linux-based routing stack while PPE handles packet classification and QoS scheduling. Use Value: Dual 10 GbE MACs and PCIe Gen3 x4 enable direct connection to 10G SFP+ modules and NVMe caching drives - eliminating external switch fabric and reducing BOM cost. | Use Scenario: 4-bay NAS appliance with hardware-accelerated encryption, RAID 5 rebuild, and simultaneous SMB/NFS/iSCSI serving. IC Role / Device Role / Timing Role: System-on-chip managing SATA 3.0 HDDs/SSDs, USB 3.0 front-panel storage, and SEC-driven AES-256 encryption pipeline. Use Value: Integrated SEC performs full-disk encryption at line rate without CPU load; SATA 3.0 + PCIe Gen3 x2 support hybrid storage tiers with sub-100 µs I/O latency. |
| Security Appliances | vCPE Gateways |
Use Scenario: Next-generation firewall performing deep packet inspection, TLS decryption, and IPSec VPN termination for remote sites. IC Role / Device Role / Timing Role: Trusted execution environment (via TrustZone) isolates firewall policy engine from untrusted traffic processing handled by PPE and SEC. Use Value: Hardware-accelerated SSL/TLS record decryption and IPsec ESP processing sustain >8 Gbps encrypted throughput - exceeding software-only alternatives by 4×. | Use Scenario: Virtualized customer premise equipment hosting VoIP, firewall, and SD-WAN functions on single hardware platform. IC Role / Device Role / Timing Role: Multicore host for KVM/QEMU VMs, with PPE enabling SR-IOV-like virtual switching and PCIe passthrough to FPGA-based acceleration. Use Value: Hardware virtualization extensions and PCIe Gen3 allow co-resident real-time VoIP stack and best-effort SD-WAN agent - meeting sub-15 ms jitter requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar networking and embedded processing applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LS1046ASN7QQB | Same quad-A72 core count and PPE/SEC blocks, but rated for 1.7 GHz max frequency and includes additional PCIe Gen3 x4 controller | Targeted at higher-bandwidth service provider gateways requiring four independent PCIe root complexes | Select LS1046ASN7QQB when >10 Gbps aggregate PCIe bandwidth or dual 10 GbE + quad PCIe endpoints are required |
| LS1023ASN7QQB | Dual-core ARM Cortex-A53, no PPE, lower DDR4 bandwidth (1600 MT/s), single 10 GbE MAC, no SEC hardware acceleration | Suitable for cost-sensitive industrial gateways where packet acceleration and crypto offload are not required | Choose LS1023ASN7QQB only for non-security, non-line-rate forwarding use cases with <5 Gbps throughput needs |
Compared with LS1046ASN7QQB and LS1023ASN7QQB, the LS1026ASN8Q1A delivers optimal balance of 10 GbE packet acceleration, hardware crypto, and thermal efficiency (≤10 W) for mid-tier networking appliances - avoiding over-specification while maintaining upgrade path to LS1046A.
Availability
LS1026ASN8Q1A is available at Aetrix Electronics and suitable for enterprise routers, network-attached storage, and security appliances requiring stable component supply, long-term lifecycle assurance, and qualified industrial temperature grade (-40°C to +105°C).
Supply support for LS1026ASN8Q1A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, IoT, and networking markets.
The QorIQ LS1026A series belongs to NXP's Layerscape family of communication processors, designed specifically for scalable, secure, and power-efficient edge networking infrastructure - from vCPE and SD-WAN appliances to industrial gateways and compact firewalls.
FAQ
What is the maximum operating frequency of the LS1026ASN8Q1A?
The LS1026ASN8Q1A operates at a maximum frequency of 1.5 GHz across all four ARM Cortex-A72 cores. This frequency is validated under industrial temperature conditions (-40°C to +105°C) with convection-cooled thermal design. The LS1026ASN8Q1A achieves >32,000 CoreMarks® at this speed while maintaining total SoC power below 10 W - making it suitable for fanless embedded networking enclosures.
Does the LS1026ASN8Q1A support hardware-accelerated IPsec and TLS processing?
Yes, the LS1026ASN8Q1A includes a dedicated Security Engine (SEC) that accelerates IPsec ESP/AH, TLS/SSL record encryption and decryption, IKEv2 key exchange, and SHA-256 hashing. It sustains >10 Gbps encrypted throughput with full protocol stack offload, freeing CPU cores for application-layer tasks. The LS1026ASN8Q1A SEC also supports high-speed XOR for RAID 5 acceleration - a capability confirmed in NXP reference manual LS1026ARM.
Is the LS1026ASN8Q1A pin-compatible with other QorIQ LS10xx processors?
Yes, the LS1026ASN8Q1A shares identical ball mapping with LS1023A, LS1043A, and LS1088A processors. This pin compatibility enables hardware reuse across dual-A53, quad-A53, and quad-A72 product families. However, voltage rail sequencing, DDR4 timing parameters, and PCIe reference clock requirements differ - so schematic and layout review against LS1026ASN8Q1A-specific design guidelines (AN5097, AN5122) remains mandatory.
What Ethernet interfaces does the LS1026ASN8Q1A provide?
The LS1026ASN8Q1A integrates two 10 GbE MACs (XFI), one 2.5 GbE MAC (2.5G SGMII), and four 1 GbE MACs (SGMII). All Ethernet interfaces support IEEE 1588v2 hardware timestamping and can be configured for SGMII, 2.5G SGMII, or XFI modes via strap pins and RCW. The LS1026ASN8Q1A does not include integrated PHYs for 10G - external PHYs (e.g., Aquantia AQR107) are required for XFI-to-Copper conversion.
Does the LS1026ASN8Q1A support DDR4 memory with ECC?
Yes, the LS1026ASN8Q1A features a dual-channel DDR4 memory controller supporting data rates up to 2400 MT/s and 64-bit bus width with 8-bit ECC. It implements on-die ECC correction and address parity checking to meet IEC 62443-3-3 reliability requirements. The LS1026ASN8Q1A supports up to 64 GB of DDR4 memory with registered DIMMs or up to 32 GB with UDIMMs - validated using Micron MT40A512M16LY-075:E components.
LS1026ASN8Q1A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 780-FBGA, FCBGA
- Series:
- QorIQ® Layerscape
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A72
- Number of Cores/Bus Width:
- 2 Core, 64-Bit
- Speed:
- 1.6GHz
- Co-Processors/DSP:
- -
- RAM Controllers:
- DDR4
- Graphics Acceleration:
- -
- Display & Interface Controllers:
- -
- Ethernet:
- 10GbE (2), 2.5GbE (1), 1GbE (4)
- SATA:
- SATA 6Gbps (1)
- USB:
- USB 3.0 (3) + PHY
- Voltage - I/O:
- -
- Operating Temperature:
- 0°C ~ 105°C
- Grade:
- -
- Qualification:
- -
- Security Features:
- Secure Boot, TrustZone®
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 780-FCPBGA (23x23)
- Additional Interfaces:
- -
LS1026ASN8Q1A FAQ
1.How can I place an order for LS1026ASN8Q1A through Aetrix?
Please submit a Request for Quotation (RFQ) for LS1026ASN8Q1A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LS1026ASN8Q1A reliable?
The price and inventory of LS1026ASN8Q1A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LS1026ASN8Q1A is usually 5 days.
3.What payment methods are accepted for LS1026ASN8Q1A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LS1026ASN8Q1A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LS1026ASN8Q1A?
LS1026ASN8Q1A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LS1026ASN8Q1A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LS1026ASN8Q1A?
For technical support, including LS1026ASN8Q1A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LS1026ASN8Q1A requirements.
6.How does Aetrix verify that LS1026ASN8Q1A is sourced from the original manufacturer or authorized distributors?
All LS1026ASN8Q1A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LS1026ASN8Q1A meets industry standards.
7.What is the process for return or replacement of LS1026ASN8Q1A?
All LS1026ASN8Q1A units undergo pre-shipment inspection (PSI). If there is an issue with LS1026ASN8Q1A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LS1026ASN8Q1A part is unused and in its original packaging.
Return procedure for LS1026ASN8Q1A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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