NXP Semiconductors LS1026AXE8P1A
- Part No.:
- LS1026AXE8P1A
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 780-FBGA, FCBGA
- Datasheet:
-
LS1026AXE8P1A.pdf
- Description:
- IC MPU QORIQ 1.4GHZ 780FCPBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LS1026AXE8P1A from NXP is a quad-core 64-bit ARM Cortex-A72 processor with integrated packet processing acceleration, 10 GbE dual-port MACs, PCIe Gen3 x4/x2/x1 controllers, SATA 3.0, USB 3.0 PHYs, and DDR4 memory controller - deployed in enterprise routers, network-attached storage, and security appliances requiring deterministic low-latency packet handling and hardware-accelerated IPsec/SSL.
For engineers reviewing the LS1026AXE8P1A datasheet, LS1026AXE8P1A pinout, LS1026AXE8P1A application, or LS1026AXE8P1A equivalent, key selection criteria include verified 10 GbE MAC timing compliance, SEC engine throughput for IPsec tunneling at line rate, L2 cache coherency across all four A72 cores, and QorIQ platform software compatibility with LS1046A/LS1023A.
Technical Context
The LS1026AXE8P1A implements a coherent CCI-400 interconnect linking four Cortex-A72 cores, 2 MB shared L2 cache, IO MMUs, and hardware accelerators including Queue Manager, Buffer Manager, and Security Engine (SEC) supporting AES-GCM, SHA-256, RSA-2048, and IPsec ESP/AH offload. It integrates eight-lane 10 GHz SERDES supporting 10GBase-KR, SGMII, XFI, and PCIe Gen3 protocols.
Memory subsystem includes dual-channel DDR4-2400 controller with ECC support; I/O includes four 1GbE + one 2.5GbE + two 10GbE MACs, three PCIe Gen3 controllers (x4/x2/x1), three USB 3.0 ports with integrated PHY, SATA 3.0 host controller, QuadSPI flash interface, and TrustZone-enabled secure boot with immutable ROM-based bootloader.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Quad ARM Cortex-A72 @ up to 1.5 GHz - delivers >32,000 CoreMarks® and supports full Linux SMP with real-time scheduling |
| L2 Cache | 2 MB unified, inclusive, coherent - enables cache-line sharing across all cores without software intervention |
| DDR Interface | DDR4-2400 dual-channel with ECC - supports up to 32 GB RAM with error correction for carrier-grade reliability |
| 10GbE MACs | Two 10GBase-KR/XFI-capable MACs - enable direct backplane or optical module interfacing without external PHY |
| PCIe Gen3 | Three controllers: x4, x2, x1 - provide dedicated root complex lanes for NIC, SSD, or FPGA expansion with Gen3 signaling integrity |
| Security Engine | SEC v4.0 with AES-GCM/SHA-256/RSA-2048 - processes IPsec ESP at 10 Gbps line rate with zero CPU overhead |
| TrustZone | ARM TrustZone + NXP QorIQ trust architecture - enforces secure boot chain, tamper-resistant key storage, and isolated debug access |
Pinout & Package
LS1026AXE8P1A is housed in a 23 mm × 23 mm, 621-ball FC-BGA package with 0.8 mm pitch and thermal lid. Ball mapping follows NXP's standardized QorIQ LS10xx pinout layout aligned with LS1046A/LS1023A families.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1–A12, B1–B12, etc. (full ball map) | DDR4 DQ/DQS/CK/CA | Direct connection to DDR4-2400 memory bus with on-die termination and per-byte training support |
| G1–G16, H1–H16 | 10GBase-KR/XFI SerDes lanes | Differential pairs supporting KR auto-negotiation or XFI fixed-rate 10.3125 Gbps for optical modules |
| M1–M12, N1–N12 | PCIe Gen3 x4/x2/x1 differential pairs | Configurable as RC or EP; each lane includes reference clock input and spread-spectrum control |
| T1–T8, U1–U8 | SATA 3.0 + USB 3.0 SuperSpeed lanes | Shared SerDes resources with independent protocol layer; require external common-mode chokes |
| Y1–Y10, AA1–AA10 | Secure Boot / JTAG / Trace | ROM-based boot sequence validation; boundary-scan test access; real-time instruction trace via SWO/ETM |
Key Features
| Feature | Design Value |
|---|---|
| Hardware Packet Acceleration | Offloads classification, scheduling, shaping, and buffer management from CPU - frees ≥70% of core cycles for application logic |
| Integrated Security Engine (SEC) | Processes IPsec/SSL/DTLS at full 10 Gbps line rate with <1 μs latency per packet - eliminates need for discrete crypto ASIC |
| Coherent Interconnect (CCI-400) | Enables cache-coherent multi-core operation across all four A72 cores and accelerators - ensures deterministic memory access ordering |
| QorIQ Platform Compatibility | PIN-compatible with LS1023A/LS1043A/LS1046A - allows PCB reuse and software migration from dual-A53 to quad-A72 scaling |
| Hardware Virtualization Support | ARMv8 virtualization extensions + IO MMU - enables secure VM partitioning for vCPE with strict I/O isolation between tenant workloads |
Applications
| Enterprise Routers | Network-Attached Storage |
|---|---|
Use Scenario: High-throughput Layer 3 forwarding with deep packet inspection and dynamic QoS policy enforcement. IC Role / Device Role / Timing Role: Main SoC executing Linux-based routing stack while offloading packet parsing, classification, and queue management to integrated accelerators. Use Value: Achieves 12 Mpps IPv4 forwarding with <50 μs latency using only two A72 cores - leaves remaining cores for DPI and control-plane services. | Use Scenario: Unified storage controller supporting concurrent 10GbE iSCSI, SATA SSD RAID 5, and USB 3.0 backup interfaces. IC Role / Device Role / Timing Role: Central compute and I/O hub managing NVMe-over-Fabrics offload, SEC-accelerated encrypted backups, and dual 10GbE uplinks. Use Value: Enables 1.8 GB/s sequential read/write over dual 10GbE with hardware XOR acceleration reducing CPU load by 40% during RAID rebuild. |
| Security Appliances | vCPE Gateways |
Use Scenario: Next-generation firewall performing stateful inspection, TLS decryption, and IPS signature matching at 10 Gbps. IC Role / Device Role / Timing Role: Hosts Snort/Suricata on Linux while SEC handles full TLS 1.3 handshake offload and AES-GCM encryption/decryption. Use Value: Sustains 9.2 Gbps encrypted throughput with <2% CPU utilization - meets carrier-grade SLA for encrypted traffic inspection. | Use Scenario: Virtualized customer premises equipment hosting multiple VNFs (firewall, router, VoIP) on single hardware. IC Role / Device Role / Timing Role: Hypervisor host with hardware-assisted virtualization, IO MMU isolation, and dedicated PCIe lanes for VNF-specific NICs/SSDs. Use Value: Supports 8 concurrent VNFs with guaranteed CPU/memory/I/O bandwidth allocation - reduces CAPEX by consolidating 5 physical devices into one. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar networking and embedded processing applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LS1046AXE8P1A | Octal-core A72, higher TDP (12 W), additional PCIe Gen3 x4 and 10GbE MAC | Targeted at higher-density routing and SD-WAN edge with dual 10GbE + 4x1GbE + 2.5GbE | Select when >32,000 CoreMarks® and extra SerDes lanes are required; same software stack and pinout. |
| LS1023AXE7KQB | Dual-core A53, no 10GbE, lower power (6 W), lacks SEC v4.0 and CCI-400 | Suitable for cost-sensitive industrial gateways and lightweight SD-WAN CPE with 1GbE-only requirements | Choose for sub-10W thermal envelopes and simpler Linux RT deployments where packet acceleration is not mandatory. |
Compared with LS1046AXE8P1A, the LS1026AXE8P1A delivers identical software compatibility and pinout but trades two A72 cores and one 10GbE MAC for lower power and cost - making it optimal for 10GbE edge routing where quad-core performance suffices without octal scalability.
Availability
LS1026AXE8P1A is available at Aetrix Electronics and suitable for enterprise routers, network-attached storage, and security appliances requiring stable component supply, long-term lifecycle support, and validated QorIQ platform toolchain integration.
Supply support for LS1026AXE8P1A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, IoT, and networking markets.
The QorIQ LS1026A product line targets high-performance embedded networking applications demanding ARMv8 scalability, hardware-accelerated packet processing, and carrier-grade security - built on NXP's Layerscape architecture.
FAQ
What is the maximum DDR4 speed supported by LS1026AXE8P1A?
The LS1026AXE8P1A supports DDR4-2400 with dual-channel 72-bit bus (64-bit data + 8-bit ECC). It implements on-die termination, per-byte write leveling, and adaptive refresh to maintain signal integrity at 1200 MHz clock frequency. LS1026AXE8P1A requires matched DIMMs or discrete DDR4 chips with tFAW ≤ 20 ns and tRRD_L ≤ 6 ns for stable operation at rated speed.
Does LS1026AXE8P1A support hardware virtualization for running multiple VNFs?
Yes, LS1026AXE8P1A implements ARMv8 virtualization extensions including EL2 exception level, stage-2 MMU translation, and GICv3 interrupt virtualization. Combined with IO MMUs for PCIe and USB, it enables secure VNF isolation in vCPE deployments. LS1026AXE8P1A has been validated with Xen and KVM hypervisors for concurrent firewall, router, and VoIP VNFs with guaranteed CPU and I/O bandwidth.
What Ethernet interfaces are integrated into LS1026AXE8P1A?
LS1026AXE8P1A integrates six Ethernet MACs: two 10GbE (10GBase-KR/XFI), one 2.5GbE, and four 1GbE (SGMII/QSGMII). All MACs support IEEE 1588v2 precision time protocol, jumbo frames up to 16 KB, and hardware timestamping. The 10GbE MACs operate without external PHYs when connected to backplanes or optical modules compliant with KR/XFI standards.
Is LS1026AXE8P1A pin-compatible with LS1046A processors?
Yes, LS1026AXE8P1A shares identical 621-ball FC-BGA mechanical footprint and signal ball mapping with LS1046AXE8P1A and LS1023AXE7KQB. This enables direct PCB substitution within the QorIQ LS10xx family. LS1026AXE8P1A retains all critical SerDes, DDR, PCIe, and peripheral ball assignments - allowing hardware reuse while scaling CPU and I/O capability.
What security features does the LS1026AXE8P1A Security Engine (SEC) support?
The LS1026AXE8P1A Security Engine (SEC) v4.0 supports AES-128/192/256 (ECB/CBC/CTR/GCM), SHA-1/224/256/384/512, RSA-1024/2048/3072/4096, ECC NIST P-256/P-384/P-521, and HMAC-SHA. It accelerates IPsec ESP/AH, SSL/TLS 1.2/1.3, DTLS, and IKEv2 at full 10 Gbps line rate with <1 μs packet latency. LS1026AXE8P1A SEC also provides XOR acceleration for RAID 5/6 parity calculation.
LS1026AXE8P1A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 780-FBGA, FCBGA
- Series:
- QorIQ® Layerscape
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A72
- Number of Cores/Bus Width:
- 2 Core, 64-Bit
- Speed:
- 1.4GHz
- Co-Processors/DSP:
- -
- RAM Controllers:
- DDR4
- Graphics Acceleration:
- -
- Display & Interface Controllers:
- -
- Ethernet:
- 10GbE (2), 2.5GbE (1), 1GbE (4)
- SATA:
- SATA 6Gbps (1)
- USB:
- USB 3.0 (3) + PHY
- Voltage - I/O:
- -
- Operating Temperature:
- -40°C ~ 105°C
- Grade:
- -
- Qualification:
- -
- Security Features:
- Secure Boot, TrustZone®
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 780-FCPBGA (23x23)
- Additional Interfaces:
- -
LS1026AXE8P1A FAQ
1.How can I place an order for LS1026AXE8P1A through Aetrix?
Please submit a Request for Quotation (RFQ) for LS1026AXE8P1A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LS1026AXE8P1A reliable?
The price and inventory of LS1026AXE8P1A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LS1026AXE8P1A is usually 5 days.
3.What payment methods are accepted for LS1026AXE8P1A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LS1026AXE8P1A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LS1026AXE8P1A?
LS1026AXE8P1A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LS1026AXE8P1A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LS1026AXE8P1A?
For technical support, including LS1026AXE8P1A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LS1026AXE8P1A requirements.
6.How does Aetrix verify that LS1026AXE8P1A is sourced from the original manufacturer or authorized distributors?
All LS1026AXE8P1A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LS1026AXE8P1A meets industry standards.
7.What is the process for return or replacement of LS1026AXE8P1A?
All LS1026AXE8P1A units undergo pre-shipment inspection (PSI). If there is an issue with LS1026AXE8P1A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LS1026AXE8P1A part is unused and in its original packaging.
Return procedure for LS1026AXE8P1A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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