NXP Semiconductors LS1026AXE8Q1A
- Part No.:
- LS1026AXE8Q1A
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 780-FBGA, FCBGA
- Datasheet:
-
LS1026AXE8Q1A.pdf
- Description:
- IC MPU QORIQ 1.6GHZ 780FCPBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LS1026AXE8Q1A from NXP is a quad-core 64-bit ARM Cortex-A72 processor with integrated packet processing acceleration, 10 GbE dual-port MACs, PCIe Gen3 x4/x2/x1 controllers, SATA 3.0, USB 3.0 PHYs, and DDR4 memory controller - deployed in enterprise routers, network-attached storage, and security appliances.
For engineers reviewing the LS1026AXE8Q1A datasheet, LS1026AXE8Q1A pinout, LS1026AXE8Q1A application, or LS1026AXE8Q1A equivalent, key selection factors include CoreMark performance (>32,000), 10 GbE + 2.5 GbE + 4×1 GbE PHY integration, hardware-accelerated packet classification/distribution, SEC-based IPsec/SSL offload, and TrustZone-enabled secure boot.
Technical Context
The LS1026AXE8Q1A implements four coherent ARM Cortex-A72 cores with 2 MB shared L2 cache and CCI-400 interconnect, supporting 64-bit Linux and real-time OS environments. It integrates dedicated accelerators for packet parsing, classification, queue management, and buffer management - decoupling data-plane tasks from CPU cores.
Its I/O subsystem includes an 8-lane 10 GHz SERDES bank partitioned into two 10 GbE SGMII/XFI interfaces, one 2.5 GbE SGMII, four 1 GbE RGMII, three PCIe Gen3 controllers (x4/x2/x1), SATA 3.0, three USB 3.0 with PHY, QuadSPI, SD/eMMC, and dual I²C - all managed via IO MMUs and hardware virtualization support.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Quad 64-bit ARM Cortex-A72 @ up to 1.5 GHz - enables high-throughput control-plane and data-plane concurrency in routing/firewall applications. |
| L2 Cache | 2 MB unified, shared, coherent - reduces memory latency for multi-threaded packet forwarding and cryptographic workloads. |
| Network Interfaces | Dual 10 GbE (XFI/SGMII), one 2.5 GbE (SGMII), four 1 GbE (RGMII) - supports line-rate forwarding across mixed-speed uplinks and downlinks. |
| PCIe | Three Gen3 controllers: x4, x2, x1 - enables direct attachment of NICs, NVMe SSDs, or FPGA accelerators without bridge chips. |
| SATA/USB | SATA 3.0 (6 Gbps) + three USB 3.0 with integrated PHY - provides local storage and external device connectivity with no external transceivers required. |
| Security Engine | SEC 5.0 with IPsec/SSL/DTLS/IKE acceleration + XOR RAID 5 offload - achieves >10 Gbps encrypted throughput while freeing CPU cycles. |
| Memory Support | DDR4-2400 dual-channel, ECC-capable - delivers bandwidth headroom for concurrent networking, storage, and security stacks. |
Pinout & Package
LS1026AXE8Q1A is housed in a 23 mm × 23 mm, 621-ball FC-BGA package with 0.8 mm pitch, RoHS-compliant and lead-free. Pin assignment follows NXP's LS1026A reference layout per document QORIQLS1046AFS REV 1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DDR4_A[0:15] | DDR4 address bus | 16-bit address lines for dual-channel DDR4-2400 interface with on-die termination control. |
| PCIe_RX[0:7]/TX[0:7] | PCIe Gen3 differential lanes | Eight high-speed serial lanes configurable as x4/x2/x1 PCIe links with integrated clock recovery and equalization. |
| SGMII0–SGMII5 | Multi-speed Ethernet PHY interface | Supports 1 GbE (RGMII/SGMII), 2.5 GbE (SGMII), and 10 GbE (XFI) via shared SERDES lanes with per-port rate negotiation. |
| USB3_DP/DM[0:2] | USB 3.0 differential pairs | Three fully integrated SuperSpeed USB 3.0 PHYs with internal VBUS detection and link training logic. |
| QSPI_IO[0:3] | Quad SPI flash interface | Four bidirectional data lines supporting single/dual/quad I/O modes for boot ROM and firmware storage. |
Key Features
| Feature | Design Value |
|---|---|
| Hardware Packet Acceleration | Offloads classification, distribution, shaping, and buffer management - enabling sustained 10 Gbps line-rate forwarding with <5% CPU utilization. |
| Integrated Security Engine (SEC) | Accelerates IPsec ESP/AH, TLS record encryption, IKEv2 key exchange, and RAID 5 XOR - delivering >10 Gbps crypto throughput at sub-10W power. |
| ARM TrustZone + QorIQ Trust Architecture | Enables secure boot chain, isolated debug access, tamper-evident key storage, and runtime attestation - meeting FIPS 140-2 Level 3 requirements. |
| Hardware Virtualization Support | ARMv8 virtualization extensions + IOMMU enable VM partitioning of PCIe, Ethernet, and USB resources - allowing independent guest OSes for control/data planes. |
| Flexible SERDES Configuration | 8-lane 10 GHz SERDES bank supports mix-and-match protocols (10G/2.5G/1G Ethernet, PCIe, SATA) - eliminating need for external retimers or protocol converters. |
Applications
| Enterprise Router | Network-Attached Storage |
|---|---|
Use Scenario: High-density branch office router aggregating 10 GbE uplink, multiple 1 GbE LAN ports, and USB 3.0 WAN failover. IC Role / Device Role / Timing Role: Main SoC executing routing stack (BGP/OSPF), managing packet forwarding via hardware accelerators, and hosting web-based management UI. Use Value: Dual 10 GbE + 4×1 GbE + USB 3.0 enables full line-rate L3 forwarding and redundant broadband backup without external PHYs or bridges. | Use Scenario: 4-bay NAS appliance with SATA 3.0 drives, 10 GbE iSCSI target, and USB 3.0 backup port. IC Role / Device Role / Timing Role: System-on-chip handling file system, SMB/NFS/iSCSI protocol stacks, disk I/O scheduling, and encrypted data paths via SEC. Use Value: Integrated SATA 3.0, dual 10 GbE, and SEC-based AES-NI acceleration deliver >900 MB/s encrypted iSCSI throughput with <8 W total SoC power. |
| Security Appliance | vCPE Platform |
Use Scenario: Unified threat management (UTM) gateway performing firewall, IPS, SSL inspection, and VPN termination. IC Role / Device Role / Timing Role: Primary processing unit running Snort/Suricata, OpenSSL, strongSwan, and Linux netfilter - with SEC offloading crypto and packet inspection engines. Use Value: Hardware-accelerated packet classification + SEC IPsec/SSL offload sustains 5+ Gbps deep packet inspection and encrypted throughput simultaneously. | Use Scenario: Carrier-grade vCPE hosting virtualized BNG, firewall, and VoIP functions on a single board. IC Role / Device Role / Timing Role: Virtualization host SoC providing CPU, memory, PCIe, and Ethernet I/O isolation across multiple VMs using ARM virtualization extensions and IOMMU. Use Value: Hardware-enforced VM separation of control plane (Linux), data plane (DPDK), and crypto (SEC) ensures deterministic latency and service assurance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar networking and embedded processing applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LS1046AXE8Q1A | Quad A72, 2 MB L2, dual 10 GbE, 3×PCIe Gen3, SEC 5.0 | Higher core count and frequency than LS1026A; adds third PCIe controller and second 10 GbE port | Select when >32,000 CoreMarks and dual 10 GbE are required; footprint-compatible but requires updated PCB layout for extra PCIe lane routing. |
| LS1023AXE7KQB | Dual A53, 1 MB L2, single 10 GbE, 2×PCIe Gen2, SEC 4.0 | Lower power (6 W), smaller package (19×19 mm), reduced SERDES flexibility | Choose for cost-sensitive edge routers or industrial gateways where 10 GbE + dual-core performance suffices and thermal envelope is constrained. |
Compared with LS1046AXE8Q1A and LS1023AXE7KQB, the LS1026AXE8Q1A offers balanced performance (32,000+ CoreMarks), dual 10 GbE, and full PCIe Gen3 support in a 23×23 mm BGA - making it optimal for mid-tier networking equipment requiring scalability without over-provisioning.
Availability
LS1026AXE8Q1A is available at Aetrix Electronics and suitable for enterprise routers, network-attached storage systems, and security appliances requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for LS1026AXE8Q1A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, IoT, and communications markets.
The QorIQ LS1026A belongs to NXP's Layerscape family of ARM-based communication processors, designed specifically for scalable, software-compatible networking and storage platforms requiring high-performance packet processing, hardware security, and multi-gigabit I/O.
FAQ
What is the maximum DDR4 speed supported by LS1026AXE8Q1A?
The LS1026AXE8Q1A supports DDR4-2400 (1200 MHz) in dual-channel configuration with ECC capability. This delivers up to 38.4 GB/s theoretical bandwidth, sufficient for concurrent 10 GbE packet buffering, storage I/O, and security processing. LS1026AXE8Q1A requires matched DDR4 modules with appropriate timing parameters per NXP's AN5427 design guide.
Does LS1026AXE8Q1A include integrated Ethernet PHYs?
No, LS1026AXE8Q1A integrates multi-rate Ethernet MACs and SERDES blocks but requires external PHYs for 1 GbE (RGMII/SGMII) and 2.5 GbE (SGMII). For 10 GbE, it supports direct XFI connection to optical modules or KR backplane interfaces - no external 10G PHY needed. LS1026AXE8Q1A does not embed analog PHY circuitry.
Is LS1026AXE8Q1A pin-compatible with LS1023A?
Yes, LS1026AXE8Q1A is pin-compatible with LS1023A, LS1043A, and LS1088A within the same 23×23 mm FC-BGA package footprint. This allows hardware reuse across dual-A53, quad-A53, quad-A72, and octal-A72 Layerscape generations - though LS1026AXE8Q1A requires updated power delivery and signal integrity validation due to higher frequency operation.
What security protocols does the integrated SEC in LS1026AXE8Q1A accelerate?
The LS1026AXE8Q1A's Security Engine (SEC 5.0) accelerates IPsec (ESP/AH), TLS/SSL record layer encryption/decryption, DTLS, IKEv1/v2 key exchange, and high-speed XOR for RAID 5. It supports AES-128/192/256, SHA-1/256/384/512, RSA-2048/3072, and ECC NIST P-256/P-384 - all executed in hardened hardware without CPU intervention.
Can LS1026AXE8Q1A run real-time operating systems like FreeRTOS or Zephyr?
Yes, LS1026AXE8Q1A supports real-time OSes including Zephyr RTOS and FreeRTOS through ARMv8-A architecture compliance and NXP's MCUXpresso SDK. While primarily optimized for Linux-based networking stacks, its Cortex-A72 cores, GIC-400 interrupt controller, and memory protection unit enable deterministic scheduling - verified in time-critical vCPE and industrial gateway deployments using LS1026AXE8Q1A.
LS1026AXE8Q1A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 780-FBGA, FCBGA
- Series:
- QorIQ® Layerscape
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A72
- Number of Cores/Bus Width:
- 2 Core, 64-Bit
- Speed:
- 1.6GHz
- Co-Processors/DSP:
- -
- RAM Controllers:
- DDR4
- Graphics Acceleration:
- -
- Display & Interface Controllers:
- -
- Ethernet:
- 10GbE (2), 2.5GbE (1), 1GbE (4)
- SATA:
- SATA 6Gbps (1)
- USB:
- USB 3.0 (3) + PHY
- Voltage - I/O:
- -
- Operating Temperature:
- -40°C ~ 105°C
- Grade:
- -
- Qualification:
- -
- Security Features:
- Secure Boot, TrustZone®
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 780-FCPBGA (23x23)
- Additional Interfaces:
- -
LS1026AXE8Q1A FAQ
1.How can I place an order for LS1026AXE8Q1A through Aetrix?
Please submit a Request for Quotation (RFQ) for LS1026AXE8Q1A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LS1026AXE8Q1A reliable?
The price and inventory of LS1026AXE8Q1A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LS1026AXE8Q1A is usually 5 days.
3.What payment methods are accepted for LS1026AXE8Q1A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LS1026AXE8Q1A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LS1026AXE8Q1A?
LS1026AXE8Q1A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LS1026AXE8Q1A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LS1026AXE8Q1A?
For technical support, including LS1026AXE8Q1A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LS1026AXE8Q1A requirements.
6.How does Aetrix verify that LS1026AXE8Q1A is sourced from the original manufacturer or authorized distributors?
All LS1026AXE8Q1A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LS1026AXE8Q1A meets industry standards.
7.What is the process for return or replacement of LS1026AXE8Q1A?
All LS1026AXE8Q1A units undergo pre-shipment inspection (PSI). If there is an issue with LS1026AXE8Q1A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LS1026AXE8Q1A part is unused and in its original packaging.
Return procedure for LS1026AXE8Q1A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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