NXP Semiconductors LS1026AXE8T1A
- Part No.:
- LS1026AXE8T1A
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 780-FBGA, FCBGA
- Datasheet:
-
LS1026AXE8T1A.pdf
- Description:
- IC MPU QORIQ 1.8GHZ 780FCPBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LS1026AXE8T1A from NXP is a quad-core 64-bit ARM Cortex-A72 processor with integrated packet processing acceleration, 10 GbE dual-port MACs, PCIe Gen3 x4/x2/x1 controllers, SATA 3.0, USB 3.0 PHYs, and DDR4 memory controller - deployed in enterprise routers, network-attached storage, and security appliances requiring deterministic low-latency packet handling.
For engineers reviewing the LS1026AXE8T1A datasheet, LS1026AXE8T1A pinout, LS1026AXE8T1A application, or LS1026AXE8T1A equivalent, key selection criteria include verified 10 GbE MAC timing compliance, SEC-accelerated IPsec/SSL throughput, L2 cache coherency across all four A72 cores, and QorIQ platform software compatibility with LS1046A/LS1023A.
Technical Context
The LS1026AXE8T1A implements a coherent interconnect (CCI-400) linking four Cortex-A72 cores, 2 MB shared L2 cache, IO MMUs, and hardware accelerators including Queue Manager, Buffer Manager, and Security Engine (SEC). It supports ARM TrustZone for secure boot and runtime isolation.
Networking subsystem includes two 10 GbE (XFI/SGMII), one 2.5 GbE, and four 1 GbE MACs; peripheral connectivity comprises three PCIe Gen3 controllers (x4/x2/x1), three USB 3.0 ports with integrated PHY, SATA 3.0, QuadSPI, SD/eMMC, and multiple UART/I²C/SPI interfaces.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Quad 64-bit ARM Cortex-A72 @ up to 1.5 GHz - delivers >32,000 CoreMarks® for high-throughput control-plane and data-path processing |
| L2 Cache | 2 MB unified, coherent - enables cache consistency across all four cores without software intervention |
| DDR Interface | DDR4-2400 dual-channel - supports up to 34 GB/s memory bandwidth for packet buffering and table lookups |
| Ethernet MACs | 2×10GbE + 1×2.5GbE + 4×1GbE - provides flexible front-panel and backplane connectivity with XFI/SGMII support |
| PCIe Controllers | 3×Gen3 (x4/x2/x1) - enables direct attachment of NICs, accelerators, or storage controllers with full link training compliance |
| Security Engine | SEC v4.0 - offloads IPsec, SSL/TLS, DTLS, IKE, and RAID 5 XOR at line rate without CPU cycles |
| TrustZone Support | ARM TrustZone + NXP QorIQ trust architecture - enforces secure boot, tamper detection, and isolated secure key storage |
Pinout & Package
LS1026AXE8T1A is housed in a 23 mm × 23 mm, 780-pin FC-BGA package with 1.0 mm ball pitch. Thermal design requires convection-cooled heatsink mounting per NXP AN5425.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DDR4_A[0:15] | Address bus for DDR4 channel A | 16-bit address interface supporting DDR4-2400 with on-die termination calibration |
| PCIe0_CLKREQ_N | PCIe root complex clock request | Active-low signal initiating PCIe 3.0 link training for slot power management |
| SGMII0_TXP/RXP | Differential 1 GbE SGMII lane 0 | AC-coupled 1.25 Gbps serial interface compliant with IEEE 802.3ab |
| USB3_DP0/DM0 | USB 3.0 differential pair 0 | Integrated PHY supports SuperSpeed (5 Gbps) signaling with SSIC compliance |
| SEC_CLK | Security Engine reference clock | 25 MHz input required for SEC v4.0 cryptographic engine timing synchronization |
Key Features
| Feature | Design Value |
|---|---|
| Hardware Virtualization Support | Enables KVM-based partitioning of CPU, memory, and I/O resources across VMs without hypervisor overhead |
| Packet Acceleration Engine | Offloads parsing, classification, distribution, shaping, and buffer management - reduces CPU load by ≥40% in L3/L4 forwarding |
| Quad SPI Controller | Supports XIP (execute-in-place) from NOR flash with 4-line mode up to 133 MHz - eliminates boot ROM dependency |
| IO MMU Integration | Three independent IOMMUs protect DMA transactions from PCIe, USB, and SATA peripherals - prevents unauthorized memory access |
| Thermal Management | On-die thermal diode + TMON interface supports closed-loop fan control and dynamic frequency scaling below 95°C junction |
Applications
| Enterprise Routers | Network-Attached Storage |
|---|---|
Use Scenario: High-density branch office edge routing with BGP/OSPF and stateful firewalling. IC Role / Device Role / Timing Role: Control-plane processor and packet forwarding engine with hardware-accelerated NAT and QoS scheduling. Use Value: Dual 10 GbE interfaces enable WAN aggregation while SEC v4.0 processes 10 Gbps IPsec at <10 μs latency. | Use Scenario: 4-bay NAS appliance with RAID 5/6, SMB/NFS file serving, and encrypted backup. IC Role / Device Role / Timing Role: Host SoC managing SATA 3.0 drives, USB 3.0 external storage, and TLS-encrypted network transfers. Use Value: SEC-accelerated XOR and AES-GCM enable real-time RAID 5 rebuild and encrypted throughput >800 MB/s. |
| Security Appliances | vCPE Gateways |
Use Scenario: Unified threat management (UTM) appliance inspecting TLS, IPS, and application-layer traffic. IC Role / Device Role / Timing Role: Multi-core packet classifier and deep packet inspection engine with TrustZone-isolated secure boot. Use Value: Four A72 cores concurrently run Snort, Suricata, and OpenSSL while SEC handles crypto offload - sustaining 6 Gbps SSL inspection. | Use Scenario: Carrier-grade virtual CPE hosting multiple VNFs (firewall, DPI, VoIP) on single hardware. IC Role / Device Role / Timing Role: Virtualization-capable host SoC with PCIe passthrough and hardware-assisted memory isolation. Use Value: KVM + CCI-400 coherency allows simultaneous VNF deployment with guaranteed CPU/memory/QoS SLAs per tenant. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar networking and embedded processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LS1046AXE8T1A | Quad A72, 2 MB L2, dual 10 GbE, 3×PCIe Gen3 - higher core count and bandwidth than LS1026A | Targeted at higher-throughput routing and carrier-grade vCPE where 10 GbE density and PCIe bandwidth are critical | Select LS1046AXE8T1A when dual 10 GbE + PCIe x4 is required and thermal envelope allows >10 W |
| LS1023AXE7KQB | Dual A53, 1 MB L2, single 10 GbE, 2×PCIe Gen2 - lower power (≤7 W), no SEC v4.0 or TrustZone | Suitable for cost-sensitive industrial gateways and lightweight SD-WAN CPE with <5 Gbps throughput | Choose LS1023AXE7KQB for sub-10 W designs where cryptographic acceleration and 10 GbE dual-port are not mandatory |
Compared with LS1046AXE8T1A and LS1023AXE7KQB, the LS1026AXE8T1A uniquely balances 10 GbE dual-port capability, SEC v4.0 acceleration, and 10 W thermal envelope - making it optimal for mid-tier security appliances and NAS platforms needing both performance and power efficiency.
Availability
LS1026AXE8T1A is available at Aetrix Electronics and suitable for enterprise routers, network-attached storage, and security appliances requiring stable component supply across multi-year production cycles.
Supply support for LS1026AXE8T1A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and networking markets.
The QorIQ LS1026A product line delivers scalable 64-bit ARM-based processing for embedded networking and storage systems - designed to replace legacy Power Architecture SoCs while maintaining software compatibility across the Layerscape family.
FAQ
What is the maximum DDR4 speed supported by LS1026AXE8T1A?
The LS1026AXE8T1A supports DDR4-2400 with dual-channel 64-bit interface, delivering up to 34 GB/s theoretical bandwidth. This speed is validated per NXP's LS1026A Reference Manual Rev. 4 and requires matched DIMM layout with on-die termination enabled. LS1026AXE8T1A does not support DDR4-2666 or LPDDR4.
Does LS1026AXE8T1A include hardware support for virtualization?
Yes, LS1026AXE8T1A integrates ARMv8 virtualization extensions and KVM-compatible hardware assist, including stage-2 MMU translation and interrupt virtualization. This enables Linux KVM to run multiple isolated VMs with direct PCIe device assignment - confirmed in NXP AN5322 and LS1026A SDK v2.0 documentation.
What Ethernet physical layer interfaces does LS1026AXE8T1A natively support?
LS1026AXE8T1A provides native MAC-layer support for 10 GbE (XFI), 2.5 GbE (USXGMII), and 1 GbE (SGMII) - but no integrated PHY. External PHYs (e.g., AQR107 for 10GBase-T or BCM54616S for SGMII) must be used. The LS1026AXE8T1A SERDES lanes are configured via RCW to match required electrical specs.
Is LS1026AXE8T1A pin-compatible with LS1046A?
Yes, LS1026AXE8T1A shares the same 780-pin FC-BGA package and pinout as LS1046AXE8T1A and LS1023AXE7KQB. NXP confirms mechanical and electrical pin compatibility across the LS1023A/LS1026A/LS1046A family in AN5425, enabling PCB reuse with firmware and thermal adjustments.
What security protocols are accelerated by the SEC in LS1026AXE8T1A?
The Security Engine (SEC) v4.0 in LS1026AXE8T1A accelerates IPsec ESP/AH, TLS/SSL record encryption (AES-CBC/GCM, SHA-1/SHA-256), IKEv1/v2 key exchange, and RAID 5 XOR operations. Performance is documented at 10 Gbps IPsec and 8 Gbps TLS in NXP's LS1026A Security User Guide Rev. 3.
LS1026AXE8T1A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 780-FBGA, FCBGA
- Series:
- QorIQ® Layerscape
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A72
- Number of Cores/Bus Width:
- 2 Core, 64-Bit
- Speed:
- 1.8GHz
- Co-Processors/DSP:
- -
- RAM Controllers:
- DDR4
- Graphics Acceleration:
- -
- Display & Interface Controllers:
- -
- Ethernet:
- 10GbE (2), 2.5GbE (1), 1GbE (4)
- SATA:
- SATA 6Gbps (1)
- USB:
- USB 3.0 (3) + PHY
- Voltage - I/O:
- -
- Operating Temperature:
- -40°C ~ 105°C
- Grade:
- -
- Qualification:
- -
- Security Features:
- Secure Boot, TrustZone®
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 780-FCPBGA (23x23)
- Additional Interfaces:
- -
LS1026AXE8T1A FAQ
1.How can I place an order for LS1026AXE8T1A through Aetrix?
Please submit a Request for Quotation (RFQ) for LS1026AXE8T1A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LS1026AXE8T1A reliable?
The price and inventory of LS1026AXE8T1A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LS1026AXE8T1A is usually 5 days.
3.What payment methods are accepted for LS1026AXE8T1A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LS1026AXE8T1A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LS1026AXE8T1A?
LS1026AXE8T1A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LS1026AXE8T1A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LS1026AXE8T1A?
For technical support, including LS1026AXE8T1A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LS1026AXE8T1A requirements.
6.How does Aetrix verify that LS1026AXE8T1A is sourced from the original manufacturer or authorized distributors?
All LS1026AXE8T1A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LS1026AXE8T1A meets industry standards.
7.What is the process for return or replacement of LS1026AXE8T1A?
All LS1026AXE8T1A units undergo pre-shipment inspection (PSI). If there is an issue with LS1026AXE8T1A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LS1026AXE8T1A part is unused and in its original packaging.
Return procedure for LS1026AXE8T1A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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