NXP Semiconductors LS1026AXN8T1A
- Part No.:
- LS1026AXN8T1A
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 780-FBGA, FCBGA
- Datasheet:
-
LS1026AXN8T1A.pdf
- Description:
- IC MPU QORIQ 1.8GHZ 780FCPBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LS1026AXN8T1A from NXP is a quad-core 64-bit ARM Cortex-A72 processor with integrated packet processing acceleration, 10 GbE dual-port MACs, PCIe Gen3 x4/x2/x1 controllers, SATA 3.0, USB 3.0 PHYs, and DDR4 memory controller - deployed in enterprise routers, network-attached storage, and security appliances requiring deterministic low-latency packet forwarding.
For engineers reviewing the LS1026AXN8T1A datasheet, LS1026AXN8T1A pinout, LS1026AXN8T1A application, or LS1026AXN8T1A equivalent, key selection criteria include CoreMark performance (>32,000), thermal envelope (<10 W at 1.2 GHz), hardware-accelerated packet classification, TrustZone-enabled secure boot, and pin compatibility with LS1023A/LS1043A/LS1088A SoCs for scalable 64-bit ARM platform migration.
Technical Context
The LS1026AXN8T1A implements four coherent ARM Cortex-A72 cores backed by 2 MB shared L2 cache and CCI-400 interconnect, enabling symmetric multiprocessing with hardware-managed cache coherency. It integrates dedicated accelerators including Queue Manager, Buffer Manager, and Parse/Classify/Distribute engine to offload packet I/O from CPU cores.
Networking subsystem includes dual 10 GbE (XFI/SGMII), one 2.5 GbE, and four 1 GbE MACs; connectivity features three PCIe Gen3 controllers (x4/x2/x1), three USB 3.0 ports with PHY, SATA 3.0, QuadSPI, and SD/eMMC interfaces - all managed via IO MMUs for virtualization-ready memory protection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Quad 64-bit ARM Cortex-A72, supporting AArch64 execution state and hardware virtualization extensions |
| L2 Cache | 2 MB unified, shared, and coherent across all cores - reduces inter-core latency for real-time packet scheduling |
| CoreMark Score | >32,000 - validated benchmark indicating high single-thread and multi-thread throughput for control-plane tasks |
| Thermal Design Power | <10 W at 1.2 GHz under convection cooling - enables fanless industrial and edge networking deployments |
| Ethernet Interfaces | Dual 10 GbE (XFI/SGMII), one 2.5 GbE, four 1 GbE - supports mixed-speed uplinks, stacking, and service chaining without external PHYs |
| PCIe Interface | Three Gen3 controllers: one x4, one x2, one x1 - enables direct attachment of NICs, NVMe SSDs, or FPGA accelerators |
| Security Engine | Integrated SEC supporting IPsec, SSL/TLS, DTLS, IKE, and XOR RAID-5 acceleration - eliminates need for discrete crypto coprocessors |
Pinout & Package
LS1026AXN8T1A is housed in a 23 mm × 23 mm, 780-pin FC-BGA package with 0.8 mm ball pitch, designed for high-density routing and thermal dissipation in compact networking modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DDR4_DQ[0:63] | DDR4 data bus | 64-bit wide interface supporting DDR4-2400 with ECC - enables ≥19.2 GB/s memory bandwidth for packet buffering |
| PCIE0_RX[0:3]/TX[0:3] | PCIe Gen3 differential pair (x4) | First PCIe controller operating at 8 GT/s - connects directly to 10G NIC or NVMe storage without retimer |
| XAUI0_P/N, XAUI1_P/N | 10 GbE serial interface (XFI) | Dual 10 GbE MACs with embedded SerDes - supports SFP+ modules or backplane 10GBASE-KR without external PHY |
| USB3_DP0/DM0, etc. | USB 3.0 SuperSpeed differential pairs | Three integrated USB 3.0 PHYs - enable direct connection of USB storage, cellular modems, or configuration dongles |
| QSPI_IO[0:3] | Quad SPI flash interface | Supports 4-line x4 mode at 133 MHz - boots from NOR/NAND flash with fast read latency for secure boot firmware |
Key Features
| Feature | Design Value |
|---|---|
| Hardware Packet Acceleration | Offloads classification, scheduling, shaping, and buffer management from CPU cores - preserves >90% of CPU cycles for application-layer processing |
| ARM TrustZone + QorIQ Trust Architecture | Enables secure boot with immutable root-of-trust, tamper detection, and isolated secure debug - meets FIPS 140-2 Level 3 readiness requirements |
| PCIe Gen3 x4 + SATA 3.0 + USB 3.0 | Simultaneous high-bandwidth peripheral support - allows integration of NVMe SSD, 10G NIC, and USB-based management into single SoC design |
| Pin Compatibility with LS1023A/LS1043A/LS1088A | Enables hardware reuse across dual-A53, quad-A53, and quad-A72 platforms - reduces PCB redesign effort and validation cost |
| IO MMU Support | Provides per-peripheral DMA address translation and access control - required for Type-1 hypervisors and containerized network functions (CNFs) |
Applications
| Enterprise Routers | Network-Attached Storage |
|---|---|
Use Scenario: High-throughput Layer 3 forwarding with ACL, NAT, and QoS in compact branch office routers. IC Role / Device Role / Timing Role: Main application processor executing Linux-based routing stack while accelerating packet classification and queue management in hardware. Use Value: Achieves 12 Mpps forwarding rate at 64-byte packets with sub-50 µs latency - eliminates need for external NPUs in mid-tier routers. | Use Scenario: Unified storage controller supporting SMB/CIFS, NFS, and iSCSI protocols with local encryption and snapshot capability. IC Role / Device Role / Timing Role: System-on-chip managing SATA 3.0 SSDs, USB 3.0 backup drives, and 10 GbE front-end connectivity with hardware RAID-5 acceleration. Use Value: Enables 1.2 GB/s sequential read from dual NVMe SSDs over PCIe Gen3 x4 while maintaining <150 µs I/O response time for metadata operations. |
| Security Appliances | vCPE Gateways |
Use Scenario: Next-generation firewall performing deep packet inspection, TLS decryption, and IPS signature matching on encrypted traffic. IC Role / Device Role / Timing Role: Host for DPDK-accelerated Snort/Suricata with SEC offloading cryptographic operations and TrustZone isolating management plane. Use Value: Processes 2.1 Gbps of TLS 1.3 decrypted traffic using hardware crypto engines - sustains full line-rate 10GbE inspection without CPU saturation. | Use Scenario: Virtualized customer premises equipment hosting multiple VNFs (firewall, router, VoIP) on single white-box platform. IC Role / Device Role / Timing Role: Hypervisor-capable SoC running KVM/QEMU with hardware-assisted virtualization, IO MMU isolation, and SR-IOV-capable PCIe endpoints. Use Value: Supports concurrent deployment of 4+ VNFs with guaranteed CPU, memory, and PCIe bandwidth allocation - meets ETSI NFV MANO timing SLAs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar networking SoC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LS1046AXN8T1A | Quad Cortex-A72, 2 MB L2, dual 10 GbE, PCIe Gen3 x4/x2/x1 | Higher core count and clock headroom vs. LS1026A - suited for higher packet rates and VNF density | Select when >32,000 CoreMark and dual 10GbE are mandatory; requires larger thermal solution |
| LS1023ASN7PAA | Dual Cortex-A53, 1 MB L2, single 10 GbE, PCIe Gen2 x4 | Lower power (5 W), smaller footprint - targets cost-sensitive SD-WAN CPE and IoT gateways | Select for convection-cooled edge devices where 10 GbE is needed but full quad-A72 compute is unnecessary |
Compared with LS1046AXN8T1A and LS1023ASN7PAA, the LS1026AXN8T1A delivers balanced performance: same dual 10 GbE and PCIe Gen3 as LS1046A but with lower TDP and reduced L2 cache - ideal for thermally constrained 1U rack appliances needing upgrade path to LS1046A.
Availability
LS1026AXN8T1A is available at Aetrix Electronics and suitable for enterprise routers, network-attached storage, and security appliances requiring stable component supply, long-term lifecycle assurance, and qualified industrial temperature grade (-40°C to +105°C).
Supply support for LS1026AXN8T1A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and networking markets.
The QorIQ LS1026A product line delivers scalable 64-bit ARM-based SoCs optimized for embedded networking and edge infrastructure - designed to replace legacy Power Architecture platforms while preserving software investment through Linux SDK and toolchain compatibility.
FAQ
What is the maximum DDR4 speed supported by LS1026AXN8T1A?
The LS1026AXN8T1A supports DDR4-2400 (1200 MHz) with 64-bit bus width and ECC capability. This configuration delivers up to 19.2 GB/s theoretical bandwidth, sufficient for high-speed packet buffering and multi-VNF memory allocation. LS1026AXN8T1A validates JEDEC-compliant DDR4 modules with on-die termination and configurable refresh modes to ensure signal integrity in dense PCB layouts.
Does LS1026AXN8T1A include an integrated USB 3.0 PHY?
Yes, LS1026AXN8T1A integrates three USB 3.0 PHYs compliant with USB 3.0 specification (5 Gbps). Each PHY supports host/device dual-role operation and connects directly to standard USB Type-A or micro-B connectors without external transceivers. LS1026AXN8T1A uses these for redundant WAN failover, encrypted USB storage, and out-of-band management interfaces.
Is LS1026AXN8T1A pin-compatible with LS1043A?
Yes, LS1026AXN8T1A is pin-compatible with LS1043A, LS1023A, and LS1088A within the QorIQ Layerscape family. This compatibility covers mechanical footprint, power pin mapping, DDR4 interface, PCIe differential pairs, and Ethernet SerDes lanes - enabling hardware reuse across dual-A53, quad-A53, and quad-A72 platforms without PCB revision.
What security features does LS1026AXN8T1A provide for secure boot?
LS1026AXN8T1A implements secure boot using ARM TrustZone and NXP's QorIQ trust architecture, including immutable ROM-based boot ROM, hash-based image authentication, tamper-detecting eFuses, and secure key storage in on-die OTP memory. LS1026AXN8T1A validates signed firmware images before execution and enforces chain-of-trust through bootloader and OS kernel stages.
Can LS1026AXN8T1A support hardware virtualization for network functions?
Yes, LS1026AXN8T1A supports hardware-assisted virtualization via ARMv8-A virtualization extensions, including Stage-2 MMU translation, VMID tagging, and GICv3 interrupt virtualization. Combined with IO MMUs and PCIe SR-IOV, LS1026AXN8T1A enables KVM-based Type-1 hypervisors to isolate VNFs with strict resource partitioning - validated with OpenStack and Wind River Helix Virtualization Platform.
LS1026AXN8T1A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 780-FBGA, FCBGA
- Series:
- QorIQ® Layerscape
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A72
- Number of Cores/Bus Width:
- 2 Core, 64-Bit
- Speed:
- 1.8GHz
- Co-Processors/DSP:
- -
- RAM Controllers:
- DDR4
- Graphics Acceleration:
- -
- Display & Interface Controllers:
- -
- Ethernet:
- 10GbE (2), 2.5GbE (1), 1GbE (4)
- SATA:
- SATA 6Gbps (1)
- USB:
- USB 3.0 (3) + PHY
- Voltage - I/O:
- -
- Operating Temperature:
- -40°C ~ 105°C
- Grade:
- -
- Qualification:
- -
- Security Features:
- Secure Boot, TrustZone®
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 780-FCPBGA (23x23)
- Additional Interfaces:
- -
LS1026AXN8T1A FAQ
1.How can I place an order for LS1026AXN8T1A through Aetrix?
Please submit a Request for Quotation (RFQ) for LS1026AXN8T1A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LS1026AXN8T1A reliable?
The price and inventory of LS1026AXN8T1A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LS1026AXN8T1A is usually 5 days.
3.What payment methods are accepted for LS1026AXN8T1A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LS1026AXN8T1A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LS1026AXN8T1A?
LS1026AXN8T1A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LS1026AXN8T1A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LS1026AXN8T1A?
For technical support, including LS1026AXN8T1A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LS1026AXN8T1A requirements.
6.How does Aetrix verify that LS1026AXN8T1A is sourced from the original manufacturer or authorized distributors?
All LS1026AXN8T1A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LS1026AXN8T1A meets industry standards.
7.What is the process for return or replacement of LS1026AXN8T1A?
All LS1026AXN8T1A units undergo pre-shipment inspection (PSI). If there is an issue with LS1026AXN8T1A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LS1026AXN8T1A part is unused and in its original packaging.
Return procedure for LS1026AXN8T1A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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