NXP Semiconductors LS1028ASE7PQA

Overview

LS1028ASE7PQA from NXP Semiconductors is a dual-core 64-bit ARM Cortex-A72 system-on-chip (SoC) with 1.5 GHz operation, 1 MB shared L2 cache with ECC, DDR4/DDR3L memory controller supporting 1.6 GT/s, and integrated TSN-capable Ethernet switch with four 2.5 Gbps SGMII ports - deployed in industrial gateways and time-sensitive networking edge devices.

For engineers reviewing the LS1028ASE7PQA datasheet, LS1028ASE7PQA pinout, LS1028ASE7PQA application, or LS1028ASE7PQA equivalent, key selection criteria include its FC-PBGA 448-ball package, dual A72 core architecture with TrustZone security, 2.5G TSN Ethernet support, eDP/DisplayPort 1.3 interface for 4Kp60 displays, and FlexSPI/eSDHC/USB 3.0 peripheral integration for embedded edge compute.

Technical Context

The LS1028ASE7PQA implements a Cache Coherent Interconnect (CCI-400) operating up to 400 MHz to maintain coherency between its two Cortex-A72 cores and shared 1 MB L2 cache. Its SerDes subsystem supports configurable high-speed interfaces including PCIe 3.0, SATA 6 Gbit/s, and multiple SGMII/QSGMII/USXGMII variants - all programmable per lane via configuration registers.

It integrates a dedicated ENETC (Ethernet Controller) with IEEE 1588v2 and TSN functionality, plus a separate TSN-capable Ethernet switch with hardware timestamping, frame preemption, and traffic shaping - enabling deterministic low-latency communication across industrial automation and IIoT applications requiring sub-microsecond timing precision.

Key Specifications

Pinout & Package

LS1028ASE7PQA uses a 448-ball Fine-Pitch Ceramic Ball Grid Array (FC-PBGA) package measuring 17 mm × 17 mm with 0.8 mm ball pitch. The package supports thermal dissipation up to 12 W TDP and includes dedicated power domains (G1VDD, OVDD, SVDD, AVDD) and ground banks for signal integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-performance edge computing applications.

Compared with LS1046ASE7QQB and i.MX8MQMEK, the LS1028ASE7PQA uniquely balances dual high-frequency A72 cores, integrated TSN switch + ENETC, and 4K display capability - making it optimal for compact, secure, time-deterministic edge nodes requiring both compute and human-machine interface.

Availability

LS1028ASE7PQA is available at Aetrix Electronics and suitable for industrial gateways, time-sensitive networking edge nodes, secure network appliances, and print/imaging controllers requiring stable component supply and long-term lifecycle support.

Supply support for LS1028ASE7PQA includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.

The LS1028A product line targets high-reliability edge computing applications demanding deterministic networking, hardware security, and rich multimedia I/O - extending NXP's QorIQ communications processor portfolio into industrial automation and IIoT infrastructure.

FAQ

What is the maximum operating frequency of the LS1028ASE7PQA?

The LS1028ASE7PQA operates at up to 1.5 GHz across both ARM Cortex-A72 cores. This frequency is validated under recommended operating conditions (junction temperature ≤105°C, VDD = 0.85 V–1.1 V). The chip includes dynamic voltage and frequency scaling (DVFS) support, allowing runtime adjustment to balance performance and power consumption in thermally constrained environments. LS1028ASE7PQA maintains full feature set-including TSN, GPU, and SerDes-across its entire rated frequency range.

Does the LS1028ASE7PQA support DDR4 memory with ECC?

Yes, the LS1028ASE7PQA integrates a 32-bit DDR4/DDR3L memory controller with full ECC support on both data and address paths. It supports DDR4-2400 (1.2 GT/s) and DDR3L-1866 (0.933 GT/s) with 8-bit or 16-bit ECC syndromes, correcting single-bit errors and detecting double-bit errors in real time. LS1028ASE7PQA's memory controller also includes write leveling, read leveling, and training sequences compliant with JEDEC standards. This ECC implementation is active during boot and runtime, ensuring data integrity for safety-critical industrial applications.

How many SerDes lanes does the LS1028ASE7PQA provide, and what protocols do they support?

The LS1028ASE7PQA provides four configurable SerDes lanes, each capable of supporting PCIe 3.0, SATA 6 Gbit/s, SGMII, QSGMII, 1000Base-KX, or USXGMII (10G-SXGMII/10G-QXGMII). These lanes are grouped into two independent SerDes blocks (SerDes 1 and SerDes 2), each with dedicated reference clocks and termination controls. LS1028ASE7PQA's SerDes subsystem supports mixed-mode operation - for example, one lane as PCIe 3.0 and another as 2.5G-SGMII - configured via RCW (Reset Configuration Word) and device tree bindings. All modes comply with applicable IEEE and PCI-SIG specifications.

What display interfaces are integrated into the LS1028ASE7PQA?

The LS1028ASE7PQA integrates a dual-mode DisplayPort 1.3 / eDP 1.4 PHY with support for HBR2 (5.4 Gbit/s) link rates and 4Kp60 resolution. It includes a dedicated LCD controller with RGB, LVDS, and MIPI DSI-compatible output timing, plus auxiliary channel (AUX CH) and hot-plug detection (HPD) signaling. LS1028ASE7PQA's display subsystem supports panel self-refresh (PSR), adaptive sync, and color space conversion (RGB/YUV), enabling direct drive of industrial-grade displays without external timing controllers. The eDP interface operates at 1.2 V or 1.8 V I/O voltage, configurable per design requirements.

Is the LS1028ASE7PQA pin-compatible with other LS10xxA series processors?

No, the LS1028ASE7PQA is not pin-compatible with other LS10xxA series processors such as LS1043A or LS1046A. While sharing the same FC-PBGA 448-ball footprint dimension (17 mm × 17 mm), the ball map, power domain assignments (e.g., G1VDD vs. OVDD), and critical I/O allocations (e.g., DDR, SerDes, eDP) differ significantly between variants. LS1028ASE7PQA requires its own unique PCB layout and power delivery network. Migration between LS10xxA parts necessitates board redesign and firmware adaptation due to differences in memory controller configuration, interrupt routing, and peripheral register maps. LS1028ASE7PQA's pinout is fixed per NXP's LS1028A/LS1018A Data Sheet Rev. 0.