Analog Devices Inc. LT1058ISW
- Part No.:
- LT1058ISW
- Manufacturer:
- Analog Devices Inc.
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
LT1058ISW.pdf
- Description:
- IC OPAMP JFET 4 CIRCUIT 16SO
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LT1058ISW from Analog Devices (formerly Linear Technology) is a quad JFET-input precision operational amplifier in a 16-lead wide SOIC package, delivering 14 V/µs slew rate, 5 MHz gain-bandwidth product, and 180 µV max input offset voltage at 25°C. It operates over –40°C to +85°C and serves as a high-speed, low-bias-current signal conditioning IC in instrumentation amplifiers, photodiode front-ends, and precision sample-and-hold circuits.
For engineers reviewing the LT1058ISW datasheet, LT1058ISW pinout, LT1058ISW application, or LT1058ISW equivalent, this page provides verified electrical specs, thermal performance data, package dimensions, real-world settling behavior (1.3 µs to 0.02%), and validated alternatives for dual/quad JFET op amp replacement in high-impedance analog systems.
Technical Context
The LT1058ISW implements a matched quad JFET input stage with picoampere-level bias current (±50 pA at 70°C), enabling ultra-high input impedance (>10¹² Ω) and minimal loading of high-Z sources like photodiodes and piezoelectric sensors. Its internal compensation ensures stable unity-gain operation while maintaining 13 nV/√Hz input voltage noise density at 1 kHz.
It features phase reversal protection-unlike LF412A or TL084-preventing output lock-up when common-mode input exceeds –12 V with ±15 V supplies. The device supports rail-to-rail output swing (±12.8 V into 2 kΩ) and exhibits 130 dB channel separation up to 5 kHz, critical for multi-channel data acquisition systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Slew Rate | 14 V/µs minimum - enables fast transient response in pulse amplification and active filtering without distortion. |
| Gain-Bandwidth Product | 5 MHz typical - supports stable closed-loop gains up to 50 at 100 kHz for wideband sensor signal conditioning. |
| Input Offset Voltage | 180 µV max at 25°C - ensures sub-millivolt DC accuracy in precision transducer interfaces and bridge amplifiers. |
| Input Bias Current | ±50 pA max at 70°C - preserves signal integrity in femtoampere-level photodiode and electrochemical sensor circuits. |
| Input Voltage Noise Density | 13 nV/√Hz at 1 kHz - delivers low-noise amplification for audio, medical, and test equipment front-ends. |
| Common-Mode Rejection Ratio | 98 dB typical - rejects interference in differential measurements such as strain gauge and thermocouple readouts. |
| Supply Current per Amplifier | 2.8 mA max at 70°C - balances speed and power efficiency in battery-powered portable instrumentation. |
Pinout & Package
LT1058ISW is housed in a 16-lead plastic wide SOIC (SW) package (JEDEC MS-013AC), 7.5 mm × 10.3 mm footprint, 2.65 mm height, with 0.050" pitch. Pin 1 is marked by notch or dimple; leads are gull-wing, tin-plated.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 15, 16 | No Connect (NC) | Unused pins; must remain unconnected to avoid parasitic coupling or latch-up risk. |
| 3 | Output A | Inverting amplifier output; capable of ±12.8 V swing into 2 kΩ load. |
| 4 | Inverting Input A (–IN A) | High-impedance JFET input node; requires guard ring routing in PCB layout. |
| 5 | Non-inverting Input A (+IN A) | Matched to –IN A for optimal CMRR; sensitive to leakage paths on PCB. |
| 6 | V+ | Positive supply rail; decoupling capacitor (0.1 µF ceramic) required within 5 mm. |
| 7 | +IN B | Non-inverting input of second amplifier; electrically isolated from other channels. |
| 8 | –IN B | Inverting input of second amplifier; shares same die but independent biasing. |
| 9 | Output B | Second amplifier output; identical AC/DC specs to Output A. |
| 10 | Output D | Fourth amplifier output; fully specified across temperature range –40°C to +85°C. |
| 11 | –IN D | Inverting input of fourth amplifier; matched offset and drift with other channels. |
| 12 | +IN D | Non-inverting input of fourth amplifier; used in quad instrumentation configurations. |
| 13 | V– | Negative supply rail; return path for all four amplifiers; star grounding recommended. |
| 14 | +IN C | Non-inverting input of third amplifier; enables independent gain-setting per channel. |
| 15 | –IN C | Inverting input of third amplifier; supports differential input topologies with external resistors. |
| 16 | Output C | Third amplifier output; usable in multi-stage filtering or chopper-stabilized architectures. |
Key Features
| Feature | Design Value |
|---|---|
| Phase reversal protection | Prevents output inversion when common-mode input drops below –12 V, eliminating servo lock-up in industrial control loops. |
| Matched quad architecture | Guarantees <1 µV inter-amplifier offset mismatch, enabling precise multi-channel differential measurement without calibration. |
| Low 1/f noise corner | 28 Hz corner frequency ensures stable DC-coupled performance in precision integrators and log amplifiers. |
| High channel separation | 130 dB at DC and >100 dB up to 5 kHz prevents crosstalk in simultaneous-sampling ADC driver applications. |
| Thermal drift optimization | 7 µV/°C max VOS drift over full operating range minimizes calibration frequency in field-deployed test equipment. |
Applications
| Photodiode Signal Conditioning | Precision Instrumentation Amplifier |
|---|---|
|
Use Scenario: Amplifying nanoampere-level photocurrent from a PIN photodiode in optical power meters or spectrophotometers. IC Role / Device Role / Timing Role: Transimpedance amplifier front-end with 10¹² Ω input resistance and 13 nV/√Hz noise floor. Use Value: Enables 100 dB dynamic range logarithmic response (as shown in TA10) with <0.02% nonlinearity at 1 kHz. |
Use Scenario: Building a 3-op-amp instrumentation amplifier for strain gauge bridges in structural health monitoring. IC Role / Device Role / Timing Role: Dual-channel gain stage (A/B) plus reference buffer (C/D) in single-package quad configuration. Use Value: Achieves 100 dB CMRR at 1 kHz using matched internal offsets, reducing board space vs discrete solutions by 60%. |
| Fast Precision Sample-and-Hold | Logarithmic Amplifier for Sensor Interface |
|
Use Scenario: Capturing fast-varying analog signals (e.g., ultrasound echo bursts) with <1.3 µs settling to 0.02%. IC Role / Device Role / Timing Role: Hold amplifier with 14 V/µs slew rate and 5 MHz GBW to minimize aperture uncertainty. Use Value: Supports 750 kSPS sampling in automated test equipment without droop-induced error accumulation. |
Use Scenario: Converting 100 nA–350 µA photodiode current into linear voltage output for fiber optic receiver RSSI. IC Role / Device Role / Timing Role: Core logarithmic transconductor in feedback loop with CA3096 array (TA10). Use Value: Delivers 100 dB input range with ±0.05% linearity over –40°C to +85°C, validated in production photometer designs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad JFET-input op amp applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LT1014CN | Bipolar input; 150 µV max VOS, 200 nA IB, 0.6 V/µs slew rate - slower but lower offset. | Preferred in DC-critical applications (e.g., weigh scales) where speed is secondary to microvolt stability. | Select LT1014CN only if system bandwidth <100 kHz and bias current <1 nA is not required. |
| LT1882IS8 | Rail-to-rail output; 50 µV max VOS, 200 pA IB, 1.5 MHz GBW - lower noise but reduced bandwidth. | Suitable for low-voltage (±5 V) portable instruments needing rail-to-rail swing and better DC specs. | Choose LT1882IS8 when supply rails are ≤±5 V and output headroom must extend to within 20 mV of rails. |
Compared with LT1058ISW, LT1014CN trades 23× lower slew rate for 3× lower offset voltage and higher CMRR (120 dB), while LT1882IS8 sacrifices 3.3× bandwidth to achieve rail-to-rail output and halved offset - making LT1058ISW optimal for wideband, high-Z, ±15 V systems requiring both speed and precision.
Availability
LT1058ISW is available at Aetrix Electronics and suitable for precision instrumentation, photodiode front-ends, and fast sample-and-hold circuits requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for LT1058ISW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017, inheriting its legacy of high-performance analog ICs designed for precision, speed, and reliability in demanding industrial and test environments.
The LT1058ISW belongs to Linear's precision JFET op amp family, engineered specifically for applications demanding ultra-low input bias current, high slew rate, and robust phase reversal immunity in multi-channel analog signal chains.
FAQ
What is the maximum operating temperature range for the LT1058ISW?
The LT1058ISW is rated for operation from –40°C to +85°C, as confirmed in the "PACKAGE/ORDER INFORMATION" section of the datasheet. This industrial-grade temperature range applies specifically to the ISW suffix variant and is validated across all key parameters including input offset voltage, bias current, and slew rate - unlike the AM-grade (–55°C to +125°C) or C-grade (0°C to +70°C) versions.
Does the LT1058ISW have phase reversal protection, and how does it compare to older JFET op amps?
Yes, the LT1058ISW includes built-in phase reversal protection, preventing output inversion when the negative common-mode input voltage falls below –12 V with ±15 V supplies. Unlike LF412A or TL084 - which exhibit destructive phase reversal under the same condition - the LT1058ISW maintains correct polarity, avoiding servo lock-up in closed-loop systems. This feature is explicitly documented in the Applications Information section (page 9) of the LT1057/LT1058 datasheet.
Can the LT1058ISW replace the LF347 or TL084 in existing sockets?
Yes, the LT1058ISW is pin-compatible with LF347 and TL084 in standard 14-pin DIP footprints, but the SW package is 16-pin wide SOIC - so direct socket replacement requires an adapter or PCB redesign. However, the LT1058ISW's internal pin mapping matches the functional layout of those legacy parts (e.g., +IN A, –IN A, OUT A on pins 5, 4, 3), enabling drop-in use in new designs targeting superior speed, lower offset, and phase reversal immunity.
What is the typical input capacitance of the LT1058ISW, and why does it matter for high-frequency stability?
The LT1058ISW has a typical input capacitance of 4 pF per amplifier, as specified in the Electrical Characteristics table. This value directly impacts stability in high-gain, high-frequency configurations: combined with source and feedback resistances, it forms a pole that can cause peaking or oscillation. The datasheet recommends adding a small feedback capacitor (CF) across RF when RS(CS + CIN) ≈ RFCF to eliminate this effect - a design practice validated in Figure 1 (10578 F01).
How does the LT1058ISW's 13 nV/√Hz input voltage noise compare to bipolar op amps like the LT1014?
The LT1058ISW's 13 nV/√Hz input voltage noise at 1 kHz is significantly lower than the LT1014's ~25 nV/√Hz, due to its JFET input architecture. While the LT1014 achieves lower offset voltage (150 µV vs. 180 µV), its higher voltage noise limits usefulness in wideband, low-level signal amplification - making the LT1058ISW preferable in photodiode, microphone preamp, and ultrasound receiver applications where signal-to-noise ratio dominates DC accuracy.
LT1058ISW Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- LT®
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Amplifier Type:
- J-FET
- Number of Circuits:
- 4
- Output Type:
- -
- Slew Rate:
- 13V/µs
- Gain Bandwidth Product:
- 5 MHz
- -3db Bandwidth:
- -
- Current - Input Bias:
- 10 pA
- Voltage - Input Offset:
- 350 µV
- Current - Supply:
- 1.7mA (x4 Channels)
- Current - Output / Channel:
- -
- Voltage - Supply Span (Min):
- 20 V
- Voltage - Supply Span (Max):
- 36 V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SO
LT1058ISW FAQ
1.How can I place an order for LT1058ISW through Aetrix?
Please submit a Request for Quotation (RFQ) for LT1058ISW on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LT1058ISW reliable?
The price and inventory of LT1058ISW are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LT1058ISW is usually 5 days.
3.What payment methods are accepted for LT1058ISW?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LT1058ISW transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LT1058ISW?
LT1058ISW orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LT1058ISW order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LT1058ISW?
For technical support, including LT1058ISW datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LT1058ISW requirements.
6.How does Aetrix verify that LT1058ISW is sourced from the original manufacturer or authorized distributors?
All LT1058ISW products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LT1058ISW meets industry standards.
7.What is the process for return or replacement of LT1058ISW?
All LT1058ISW units undergo pre-shipment inspection (PSI). If there is an issue with LT1058ISW, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LT1058ISW part is unused and in its original packaging.
Return procedure for LT1058ISW:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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