Analog Devices Inc. LT1113CS8#PBF
- Part No.:
- LT1113CS8#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
LT1113CS8#PBF.pdf
- Description:
- IC OPAMP JFET 2 CIRCUIT 8SO
- Quantity:
- Payment:

- Shipping:

Inventory:498
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Product details
Overview
LT1113CS8#PBF from Analog Devices (formerly Linear Technology) is a dual low-noise, precision JFET-input operational amplifier in an 8-lead plastic SOIC package. It delivers 4.5nV/√Hz input voltage noise at 1kHz, 0.4mV max input offset voltage, and 5.6MHz gain bandwidth - optimized for high-impedance capacitive transducer amplification including hydrophones and piezoelectric accelerometers.
For engineers reviewing the LT1113CS8#PBF datasheet, LT1113CS8#PBF pinout, LT1113CS8#PBF application, or LT1113CS8#PBF equivalent, key selection criteria include verified 100% tested voltage noise, guaranteed matching specifications for instrumentation amplifier front ends, ±5V to ±15V dual-supply operation, and industry-standard SO-8 pinout compatibility with OPA2111/OPA2604 replacements.
Technical Context
The LT1113CS8#PBF employs matched JFET differential input stages with picoampere bias currents (≤450pA warmed up) and ultra-low voltage noise to preserve signal integrity in high-Z sensor interfaces. Its design eliminates phase reversal beyond common-mode limits and supports stable unity-gain operation with ≥1000pF capacitive loads.
It provides guaranteed matching parameters - including ∆VOS ≤2.5mV, ∆CMRR ≥81dB, and ∆PSRR ≥82dB - enabling precise two-op-amp instrumentation topologies without external trimming. All amplifiers are 100% tested for voltage noise, slew rate (≥2.3V/µs), and gain bandwidth (≥4.0MHz).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Noise | 4.5nV/√Hz at 1kHz - enables detection of sub-µV signals from high-impedance transducers |
| Input Offset Voltage | 0.4mV max (±5V supply) - reduces DC error in precision DC-coupled front ends |
| Gain Bandwidth Product | 5.6MHz typical - supports stable closed-loop gains up to 100 with >100kHz bandwidth |
| Supply Voltage Range | ±5V to ±15V - allows flexible low-power (±5V) or high-dynamic-range (±15V) operation |
| Input Bias Current | 450pA max (warmed up) - minimizes IR drop errors with transducer impedances up to 100MΩ |
| Channel Separation | 130dB at 10Hz - prevents crosstalk in dual-channel instrumentation systems |
| Common-Mode Rejection | 98dB typical - maintains accuracy when amplifying small differential signals in noisy environments |
Pinout & Package
LT1113CS8#PBF is housed in an 8-lead plastic SOIC (SO-8) package with standard industry pinout and θJA = 190°C/W. The package is RoHS-compliant and lead-free (Pb-free finish).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | OUT A | Amplifier A output - drives 10kΩ load to ±13.8V swing with ±15V supplies |
| 2 | –IN A | Inverting input of Amplifier A - high-impedance JFET node (RIN ≥1011Ω) |
| 3 | +IN A | Noninverting input of Amplifier A - matched to Pin 2 for CMRR optimization |
| 4 | V– | Negative supply rail - accepts –5V to –15V; supports rail-to-rail input common-mode range |
| 5 | V+ | Positive supply rail - accepts +5V to +15V; powers both amplifiers independently |
| 6 | OUT B | Amplifier B output - electrically isolated from OUT A; no crosstalk above 126dB |
| 7 | –IN B | Inverting input of Amplifier B - matched to Pin 2 for ∆VOS ≤2.5mV across channels |
| 8 | +IN B | Noninverting input of Amplifier B - symmetric layout ensures thermal tracking with Pin 3 |
Key Features
| Feature | Design Value |
|---|---|
| 100% tested voltage noise | Guarantees ≤6nV/√Hz max at 1kHz - eliminates screening for low-noise applications |
| Matched dual architecture | ∆VOS ≤2.5mV and ∆CMRR ≥81dB - enables high-accuracy 3-op-amp instrumentation amps without trimming |
| Phase-reversal immunity | Operates cleanly beyond VCM limits (e.g., ±5.2V on ±5V rails) - prevents servo lock-up |
| Capacitive load drive | Stable with ≥1000pF loads at unity gain - simplifies filtering without isolation resistors |
| Low warm-up drift | Offset voltage drift <15µV/°C - maintains calibration stability over temperature cycling |
Applications
| Hydrophone Signal Conditioning | Piezoelectric Accelerometer Front End |
|---|---|
Use Scenario: Amplifying weak acoustic signals from underwater hydrophones with source impedances >10MΩ and capacitances 100pF–5000pF. IC Role / Device Role / Timing Role: Primary low-noise charge/voltage amplifier in first-stage signal conditioning. Use Value: 4.5nV/√Hz noise floor and 450pA max bias current enable >100dB SNR at 1kHz with 100MΩ transducer impedance. | Use Scenario: Conditioning output of high-sensitivity piezoelectric accelerometers used in structural health monitoring. IC Role / Device Role / Timing Role: Dual-channel transimpedance amplifier converting charge output to low-impedance voltage. Use Value: Matched ∆VOS ≤2.5mV and ∆CMRR ≥81dB ensure <0.01% gain error in differential acceleration measurement. |
| Photocurrent Amplification | Instrumentation Amplifier Core |
Use Scenario: Converting nanoamp-level photocurrents from photodiodes into measurable voltage outputs. IC Role / Device Role / Timing Role: Transimpedance amplifier with feedback network defining gain and bandwidth. Use Value: 1011Ω input resistance and 10pA max offset current minimize dark-current-induced errors. | Use Scenario: Serving as matched pair in 3-op-amp instrumentation amplifier topology for medical sensor readout. IC Role / Device Role / Timing Role: Dual amplifier providing matched gain blocks and common-mode rejection enhancement. Use Value: Guaranteed ∆PSRR ≥82dB and ∆CMRR ≥81dB reduce power-supply and EMI-induced measurement offsets by >20dB vs discrete solutions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual low-noise JFET op amp applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| OPA2111AP | Higher 1/f corner (100Hz vs 120Hz), 6.5nV/√Hz typical noise, no guaranteed matching specs | Lacks ∆VOS/∆CMRR guarantees - requires external trimming for precision instrumentation | Select when legacy DIP footprint required and matching is not critical |
| OPA2604AU | Lower GBW (2.7MHz), higher supply current (8mA vs 6.25mA), 5.5nV/√Hz typical noise | Reduced bandwidth limits use in >100kHz active filters or fast settling applications | Select for lower-cost SO-8 replacement where 5.6MHz GBW is not required |
Compared with OPA2111AP and OPA2604AU, the LT1113CS8#PBF offers superior noise performance (4.5nV/√Hz), guaranteed channel matching, and wider supply range (±5V to ±15V), making it optimal for high-precision, high-Z sensor front ends demanding minimal post-calibration.
Availability
LT1113CS8#PBF is available at Aetrix Electronics and suitable for hydrophone signal conditioning, piezoelectric accelerometer front ends, and instrumentation amplifier core circuits requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for LT1113CS8#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains full product support, datasheet documentation, and application engineering for legacy Linear parts including the LT1113 family.
The LT1113CS8#PBF belongs to Linear's precision analog amplifier product line, designed specifically for low-noise, high-input-impedance sensor interface applications where JFET input characteristics and matched dual performance are essential.
FAQ
What is the maximum guaranteed input offset voltage for LT1113CS8#PBF at ±5V supply?
The LT1113CS8#PBF has a maximum guaranteed input offset voltage of 1.5mV at ±5V supply per the datasheet's "Electrical Characteristics" table for the C-grade (–40°C to 85°C). This specification applies across the full operating temperature range and is 100% tested during production screening.
Does LT1113CS8#PBF support operation from ±5V supplies?
Yes, the LT1113CS8#PBF is fully specified and guaranteed for operation from ±5V supplies. Key parameters including input offset voltage, gain bandwidth (≥4.0MHz), and supply current (5.3–6.5mA per amplifier) are explicitly characterized at ±5V in the datasheet's Electrical Characteristics tables.
Is LT1113CS8#PBF pin-compatible with OPA2111 or OPA2604?
Yes, the LT1113CS8#PBF uses the industry-standard SO-8 pinout and is pin-compatible with OPA2111AP (DIP-8) and OPA2604AU (SO-8). It serves as a direct functional replacement with improved noise performance (4.5nV/√Hz vs 6.5nV/√Hz) and guaranteed matching specifications not offered by those alternatives.
What is the thermal resistance (θJA) of the LT1113CS8#PBF package?
The LT1113CS8#PBF in its 8-lead plastic SOIC package has a junction-to-ambient thermal resistance (θJA) of 190°C/W, as specified in the "Package Description" section of the datasheet. This value assumes standard JEDEC 2-layer board conditions and is critical for calculating die temperature rise under load.
Can LT1113CS8#PBF drive large capacitive loads without oscillation?
Yes, the LT1113CS8#PBF is unconditionally stable for gains ≥1 with capacitive loads up to 1000pF, as confirmed in the datasheet's "Features" and "Applications Information" sections. This eliminates the need for isolation resistors in filter or cable-driving configurations.
LT1113CS8#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- LT®
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Amplifier Type:
- J-FET
- Number of Circuits:
- 2
- Output Type:
- -
- Slew Rate:
- 3.9V/µs
- Gain Bandwidth Product:
- 5.6 MHz
- -3db Bandwidth:
- -
- Current - Input Bias:
- 300 pA
- Voltage - Input Offset:
- 550 µV
- Current - Supply:
- 5.3mA (x2 Channels)
- Current - Output / Channel:
- -
- Voltage - Supply Span (Min):
- 9 V
- Voltage - Supply Span (Max):
- 40 V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SO
LT1113CS8#PBF FAQ
1.How can I place an order for LT1113CS8#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LT1113CS8#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LT1113CS8#PBF reliable?
The price and inventory of LT1113CS8#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LT1113CS8#PBF is usually 5 days.
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LT1113CS8#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LT1113CS8#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LT1113CS8#PBF?
For technical support, including LT1113CS8#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LT1113CS8#PBF requirements.
6.How does Aetrix verify that LT1113CS8#PBF is sourced from the original manufacturer or authorized distributors?
All LT1113CS8#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LT1113CS8#PBF meets industry standards.
7.What is the process for return or replacement of LT1113CS8#PBF?
All LT1113CS8#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LT1113CS8#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LT1113CS8#PBF part is unused and in its original packaging.
Return procedure for LT1113CS8#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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