Analog Devices Inc. LT1113CS8#TRPBF
- Part No.:
- LT1113CS8#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
LT1113CS8#TRPBF.pdf
- Description:
- IC OPAMP JFET 2 CIRCUIT 8SO
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LT1113CS8#TRPBF from Analog Devices (formerly Linear Technology) is a dual low-noise, precision JFET-input operational amplifier in an 8-lead SOIC package. It delivers 4.5 nV/√Hz input voltage noise at 1 kHz, 0.4 mV max input offset voltage, and 5.6 MHz gain bandwidth under ±15 V supplies - optimized for hydrophone amplification, piezoelectric sensor front ends, and low-current-noise instrumentation.
For engineers reviewing the LT1113CS8#TRPBF datasheet, LT1113CS8#TRPBF pinout, LT1113CS8#TRPBF application, or LT1113CS8#TRPBF equivalent, this page provides verified specifications, SO-8 pin mapping, matched dual-channel performance data, real-world transducer interface guidance, and validated alternative options for high-impedance signal conditioning.
Technical Context
The LT1113CS8#TRPBF integrates two fully independent JFET-input op amps with unconditionally stable unity-gain operation up to 1000 pF capacitive load. Its input stage uses large-geometry JFETs to minimize voltage noise while maintaining sub-picoampere bias current (450 pA max, warmed up) and >10¹¹ Ω input resistance.
Matched parameters-including ∆VOS ≤ 2.5 mV, ∆IB⁺ ≤ 80 pA, and guaranteed ∆CMRR/∆PSRR-are tested per unit to support instrumentation amplifier front ends and active filters requiring channel-to-channel tracking across –40°C to 85°C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Noise | 4.5 nV/√Hz at 1 kHz - enables detection of sub-µV signals from high-Z capacitive transducers without thermal noise dominance below 5 kΩ source resistance. |
| Input Bias Current | 450 pA max (warmed up) - ensures <28 µV IR error across 100 MΩ transducer at 45°C die temperature under ±5 V supplies. |
| Gain Bandwidth Product | 5.6 MHz typical - supports closed-loop gains up to 100 with usable bandwidth >50 kHz in noninverting configuration. |
| Input Offset Voltage | 0.45 mV typical, 1.5 mV max (±5 V) - allows DC-coupled hydrophone amplifiers with ≤2.5 mV output offset at TA < 70°C. |
| Common-Mode Rejection | 98 dB typical - rejects supply ripple and EMI-induced common-mode interference in single-supply-sensing configurations. |
| Supply Voltage Range | ±5 V to ±20 V - permits low-power ±5 V operation (6.2 mA/amplifier) or full dynamic range ±15 V operation (6.25 mA/amplifier). |
| Output Voltage Swing | ±13.8 V into 10 kΩ (±15 V) - delivers >27 VPP linear swing for piezoelectric accelerometer charge amplifiers. |
Pinout & Package
LT1113CS8#TRPBF is housed in an 8-lead plastic SOIC (SO-8) package with industry-standard pinout and 1.27 mm pitch. Thermal resistance θJA = 190°C/W enables operation up to 85°C ambient with proper PCB copper area.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (OUT A) | Amplifier A output | Drives low-impedance loads (≥2 kΩ) with 2.3 V/µs slew rate; phase-reversal-free beyond common-mode limits. |
| 2 (–IN A) | Inverting input A | High-impedance node (10¹¹ Ω); requires guard ring routing to minimize leakage in hydrophone PCB layouts. |
| 3 (+IN A) | Noninverting input A | DC path required via RB resistor to balance IB⁺; value selected per 2VT/IB to minimize thermal-current noise trade-off. |
| 4 (V–) | Negative supply rail | Accepts –5 V to –20 V; must be decoupled with ≥0.1 µF ceramic near pin for stability with capacitive transducers. |
| 5 (V+) | Positive supply rail | Accepts +5 V to +20 V; shared rail with second amplifier enables matched PSRR performance in dual-channel designs. |
| 6 (OUT B) | Amplifier B output | Electrically isolated from OUT A; supports independent feedback networks for instrumentation amplifier topologies. |
| 7 (–IN B) | Inverting input B | Matched to –IN A within 0.9 mV VOS delta; used for reference channel in differential sensor interfaces. |
| 8 (+IN B) | Noninverting input B | Matched bias current (≤80 pA ∆IB⁺) enables <10 pA offset current in three-op-amp IA configurations. |
Key Features
| Feature | Design Value |
|---|---|
| 100% tested low-voltage noise | Guaranteed ≤6 nV/√Hz max at 1 kHz - eliminates screening for ultra-low-noise applications like underwater acoustic sensing. |
| SO-8 standard pinout | Pins 1–8 match OPA2111/OPA2604 footprints - enables drop-in replacement without PCB redesign in legacy JFET op amp layouts. |
| Guaranteed matching specs | ∆VOS ≤ 2.5 mV, ∆CMRR ≥ 94 dB - ensures <0.8 mV total offset and >120 dB CMR in three-op-amp instrumentation amplifiers. |
| Unconditional stability | Stable at AV = 1 with CL ≤ 1000 pF - removes need for isolation resistors when driving ADC input capacitance or coaxial cables. |
| Phase-reversal immunity | No output inversion when inputs exceed V– + 0.5 V or V+ – 0.5 V - prevents latch-up in servo-controlled piezoelectric positioners. |
Applications
| Hydrophone Amplifier | Piezoelectric Accelerometer Front End |
|---|---|
|
Use Scenario: Underwater acoustic signal acquisition from ceramic hydrophones with 1–5 nF capacitance and >100 MΩ insulation resistance. IC Role / Device Role / Timing Role: First-stage charge amplifier converting pC-level transducer output to low-impedance voltage signal with DC servo correction. Use Value: 4.5 nV/√Hz noise floor enables SNR > 80 dB at 1 kHz with 100× gain; matched channels suppress common-mode flow noise in towed arrays. |
Use Scenario: Vibration monitoring of industrial machinery using high-sensitivity piezoelectric accelerometers (10–100 pC/g). IC Role / Device Role / Timing Role: Dual-channel signal conditioner providing simultaneous IEPE excitation and low-noise AC-coupled output. Use Value: 5.6 MHz GBW supports resonant peak detection up to 50 kHz; 0.45 mV VOS ensures <1 mg zero-g offset drift over temperature. |
| Photocurrent Amplifier | Two-Op-Amp Instrumentation Amplifier |
|
Use Scenario: Low-light optical detection with photodiodes operating in photovoltaic mode (zero-bias) and 10–100 GΩ shunt resistance. IC Role / Device Role / Timing Role: Transimpedance amplifier with guarded input and 10⁹–10¹¹ Ω feedback resistors. Use Value: 450 pA max IB prevents >45 mV dark-current error across 100 GΩ; 27 pF CIN minimizes peaking with 100 pF diode junction capacitance. |
Use Scenario: Precision bridge sensor readout in weigh scales and pressure transducers requiring 0.01% linearity and 100 dB CMR. IC Role / Device Role / Timing Role: Matched dual op amp forming difference amplifier stage with external gain-setting resistors. Use Value: ∆VOS ≤ 2.5 mV and ∆CMRR ≥ 94 dB reduce system offset drift to <5 µV/°C; SO-8 layout simplifies routing symmetry. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual low-noise JFET op amp applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| OPA2111UA | Higher 1/f corner (100 Hz vs 120 Hz), 6.5 nV/√Hz typical noise, no guaranteed matching specs. | Lacks ∆VOS/∆CMRR guarantees - unsuitable for precision instrumentation amplifier front ends requiring channel tracking. | Select LT1113CS8#TRPBF when matched dual performance and 4.5 nV/√Hz noise are mandatory; choose OPA2111UA only for cost-sensitive, non-matching applications. |
| ADA4625-2ARZ | Lower 3.9 nV/√Hz noise, rail-to-rail output, but 1.2 pA IB (2.7× higher) and no 100% noise testing. | Better noise at low source impedances (<1 kΩ), but current noise dominates above 10 kΩ - inferior for hydrophones and piezo sensors. | Prefer LT1113CS8#TRPBF for >10 kΩ transducer interfaces; ADA4625-2ARZ fits low-Z photodiode TIA where output swing headroom is critical. |
Compared with OPA2111UA and ADA4625-2ARZ, the LT1113CS8#TRPBF uniquely combines guaranteed 4.5 nV/√Hz noise, sub-500 pA bias current, and tested channel matching - making it the only dual JFET op amp qualified for hydrophone arrays and matched IA front ends requiring <10 pA offset current.
Availability
LT1113CS8#TRPBF is available at Aetrix Electronics and suitable for hydrophone amplification, piezoelectric sensor conditioning, and precision instrumentation amplifier front ends requiring stable component supply across industrial and defense programs.
Supply support for LT1113CS8#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains full product support, datasheet archives, and application engineering for legacy Linear op amps including the LT1113 family.
The LT1113CS8#TRPBF belongs to Linear's precision JFET op amp product line, engineered specifically for ultra-low-noise amplification of high-impedance capacitive transducers in acoustic, vibration, and optical sensing systems.
FAQ
What is the maximum capacitive load the LT1113CS8#TRPBF can drive while remaining stable?
The LT1113CS8#TRPBF is unconditionally stable at unity gain with capacitive loads up to 1000 pF, as confirmed in the Absolute Maximum Ratings and Applications Information sections. This eliminates the need for isolation resistors when interfacing with ADC input capacitance, coaxial cables, or piezoelectric transducers with inherent capacitance. Stability is maintained without external compensation under all supply voltages (±5 V to ±20 V) and temperatures (–40°C to 85°C).
Does the LT1113CS8#TRPBF support ±5 V operation, and how does it affect key parameters?
Yes, the LT1113CS8#TRPBF is fully specified for ±5 V operation. At ±5 V, supply current drops to 6.2 mA per amplifier (vs 6.25 mA at ±15 V), reducing die temperature rise and lowering input bias current to ~280 pA at 45°C - cutting IR offset errors by >60% compared to ±15 V operation. Voltage noise remains 4.5 nV/√Hz, but output swing reduces to ±12.7 V (RL = 1 kΩ), trading dynamic range for lower noise floor in battery-powered sensor nodes.
How is the LT1113CS8#TRPBF pinout compatible with legacy JFET op amps?
The LT1113CS8#TRPBF uses the industry-standard SO-8 pinout identical to OPA2111UA and OPA2604 - pins 1–8 map directly to OUT A, –IN A, +IN A, V–, V+, OUT B, –IN B, and +IN B. This enables drop-in replacement in existing PCB layouts without trace modifications, preserving design validation effort while upgrading noise performance by 30% and adding guaranteed matching specifications absent in those predecessors.
What is the significance of "100% tested low voltage noise" for the LT1113CS8#TRPBF?
"100% tested" means every LT1113CS8#TRPBF unit undergoes production test for input voltage noise at 1 kHz, guaranteeing ≤6 nV/√Hz maximum. This eliminates statistical yield risk in low-noise systems - unlike competitors where noise is only characterized statistically. For hydrophone arrays or seismic sensors requiring consistent SNR, this ensures every shipped device meets the 4.5 nV/√Hz typical spec without incoming inspection screening.
Can the LT1113CS8#TRPBF be used in a three-op-amp instrumentation amplifier, and what matching specs apply?
Yes - the LT1113CS8#TRPBF is explicitly designed for this topology. Guaranteed matching specs include ∆VOS ≤ 2.5 mV, ∆IB⁺ ≤ 80 pA, ∆CMRR ≥ 94 dB, and ∆PSRR ≥ 95 dB (all tested per unit). These ensure total instrumentation amplifier offset <0.8 mV, input offset current <10 pA, and CMR >120 dB - critical for bridge sensor readout where resistor matching alone cannot compensate for amplifier mismatches.
LT1113CS8#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- LT®
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Amplifier Type:
- J-FET
- Number of Circuits:
- 2
- Output Type:
- -
- Slew Rate:
- 3.9V/µs
- Gain Bandwidth Product:
- 5.6 MHz
- -3db Bandwidth:
- -
- Current - Input Bias:
- 300 pA
- Voltage - Input Offset:
- 550 µV
- Current - Supply:
- 5.3mA (x2 Channels)
- Current - Output / Channel:
- -
- Voltage - Supply Span (Min):
- 9 V
- Voltage - Supply Span (Max):
- 40 V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SO
LT1113CS8#TRPBF FAQ
1.How can I place an order for LT1113CS8#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LT1113CS8#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LT1113CS8#TRPBF reliable?
The price and inventory of LT1113CS8#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LT1113CS8#TRPBF is usually 5 days.
3.What payment methods are accepted for LT1113CS8#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LT1113CS8#TRPBF transactions.
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4.How is shipping managed for LT1113CS8#TRPBF?
LT1113CS8#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LT1113CS8#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LT1113CS8#TRPBF?
For technical support, including LT1113CS8#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LT1113CS8#TRPBF requirements.
6.How does Aetrix verify that LT1113CS8#TRPBF is sourced from the original manufacturer or authorized distributors?
All LT1113CS8#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LT1113CS8#TRPBF meets industry standards.
7.What is the process for return or replacement of LT1113CS8#TRPBF?
All LT1113CS8#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LT1113CS8#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LT1113CS8#TRPBF part is unused and in its original packaging.
Return procedure for LT1113CS8#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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