Analog Devices Inc. LT1236CCS8-10#PBF
- Part No.:
- LT1236CCS8-10#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Voltage Reference
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
LT1236CCS8-10#PBF.pdf
- Description:
- IC VREF PRECISION 0.1% 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:1,170
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LT1236CCS8-10#PBF from Analog Devices (acquired Linear Technology) is a precision 10V voltage reference IC featuring ultra-low 15ppm/°C max temperature coefficient, 0.01% (100ppm) initial accuracy, and <6µVP-P (0.1Hz–10Hz) output noise. It operates in both series and shunt modes, sources/sinks ±10mA, and delivers stable 10V output for high-resolution ADC/DAC calibration in test equipment and inertial navigation systems.
For engineers reviewing the LT1236CCS8-10#PBF datasheet, LT1236CCS8-10#PBF pinout, LT1236CCS8-10#PBF application, or LT1236CCS8-10#PBF equivalent, key selection criteria include its 10V output stability under load/line variation, buried zener architecture enabling low hysteresis (<5ppm), and SO-8 package compatibility with AD586/AD587 footprints for drop-in replacement in legacy precision analog designs.
Technical Context
The LT1236CCS8-10#PBF uses a subsurface buried zener diode structure-eliminating surface-breakdown noise and drift-to achieve superior long-term stability (30ppm/1000hrs) and thermal hysteresis performance (<5ppm). Its dual-mode operation (series/shunt) enables flexible system integration: as a 3-terminal series reference with 1V min input-output differential, or as a 2-terminal shunt regulator with 1.5mA min current requirement.
Unlike bandgap references, it avoids on-chip heaters while maintaining 2–5ppm/°C typical TC across grades; the "C" grade specifies 10–15ppm/°C max over 0°C to 70°C. Trim pin functionality (12kΩ impedance, 70:1 attenuation) allows ±10mV fine adjustment of the 10V output without degrading TC beyond 1ppm/°C in the "A" variant-though the "C" grade supports full ±0.7% trim range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | 10.000V ±10mV (LT1236C-10 grade); enables direct full-scale calibration of 10V-range 16-bit DACs with ≤0.01% gain error. |
| Temp Coefficient | 10–15ppm/°C max (0°C to 70°C); contributes ≤0.4LSB error in 12-bit systems over 40°C span, meeting stringent metrology requirements. |
| Noise (0.1–10Hz) | <6µVP-P; corresponds to <1ppm of 10V output-critical for low-frequency precision measurements in digital voltmeters. |
| Line Regulation | 0.5–2ppm/V (14.5–40V input); ensures <20µV output shift across 25V input swing, supporting unregulated supply rails. |
| Load Regulation | 12–25ppm/mA sourcing; maintains <250µV error at 10mA load, allowing direct drive of op-amp bias networks without buffering. |
| Ripple Rejection | >100dB at 150Hz; suppresses switching supply noise to sub-µV levels, essential for clean reference in mixed-signal SoCs. |
| Long-Term Stability | 30ppm/1000hrs non-cumulative; guarantees minimal calibration drift in field-deployed instrumentation over 1+ year. |
Pinout & Package
LT1236CCS8-10#PBF is housed in an 8-lead plastic SOIC (SO-8) package with standard JEDEC MS-012AC dimensions (3.9mm × 4.9mm × 1.75mm). Pins 1, 3, 4, 6, and 7 are internally connected NC terminals-no external circuitry should be attached. Pin 5 is the TRIM terminal for output voltage adjustment.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 (NC) | No Connect | Internally bonded; floating-must remain unconnected to avoid parasitic coupling or thermal stress. |
| Pin 2 (VIN) | Input Supply | Accepts 11.5–40V; minimum 1V headroom required for regulation-enables use with 12V/15V industrial rails. |
| Pin 3 (NC) | No Connect | Internally bonded; floating-must remain unconnected to prevent ground loop errors in Kelvin sensing. |
| Pin 4 (GND) | Ground Reference | Carries only ~1mA quiescent current; serves as low-noise sense point for Kelvin connections in precision layouts. |
| Pin 5 (TRIM) | Voltage Adjustment | 12kΩ impedance, 70:1 attenuation; ±10mV trim range achievable with 10kΩ pot-allows factory or field calibration without TC penalty. |
| Pin 6 (NC) | No Connect | Internally bonded; floating-must remain unconnected to avoid compromising noise performance. |
| Pin 7 (NC) | No Connect | Internally bonded; floating-must remain unconnected to maintain specified thermal regulation behavior. |
| Pin 8 (VOUT) | Reference Output | Delivers regulated 10V; sources/sinks ±10mA; stable with 0–1000pF capacitive loads-supports direct op-amp driving. |
Key Features
| Feature | Design Value |
|---|---|
| Buried zener architecture | Eliminates surface breakdown noise and drift-enables <6µVP-P low-frequency noise and 30ppm/1000hrs long-term stability. |
| Dual-mode operation | Functions as 3-terminal series reference (VIN–GND–VOUT) or 2-terminal shunt regulator (VOUT–GND)-reduces BOM count in multi-rail systems. |
| Pin compatibility with AD586/AD587 | SO-8 footprint match enables drop-in replacement in existing designs-avoids PCB rework during upgrade to lower-drift references. |
| 100% noise tested | Guarantees <6µVP-P (0.1–10Hz) performance per unit-critical for production test equipment requiring validated noise floors. |
| High ripple rejection (>100dB) | Attenuates 150Hz switching noise by >100,000×-enables direct use with SMPS supplies in portable instrumentation. |
Applications
| High-Resolution Data Acquisition | Precision Regulator Feedback |
|---|---|
Use Scenario: 16-bit SAR ADC in automated test equipment digitizing sensor signals with ±0.5LSB total error budget. IC Role / Device Role / Timing Role: Primary 10V reference for ADC internal DAC and external signal conditioning op-amps. Use Value: 15ppm/°C max TC and <6µVP-P noise ensure <0.25LSB temperature-induced error and sub-LSB noise floor over 0–70°C. | Use Scenario: Feedback node in ultra-stable 10V linear regulator powering FPGA I/O banks requiring <10ppm voltage tolerance. IC Role / Device Role / Timing Role: Precision voltage setpoint generator referenced to GND, driving error amplifier input. Use Value: 12–25ppm/mA load regulation enables direct connection to op-amp input-no buffer needed, reducing component count and thermal drift. |
| Inertial Navigation Systems | Digital Voltmeters |
Use Scenario: Biasing gyroscope and accelerometer front-end amplifiers in aerospace IMUs operating over –40°C to +85°C. IC Role / Device Role / Timing Role: Dual-rail reference source (±10V) via external inverting stage, providing common-mode stability for differential sensors. Use Value: <5ppm thermal hysteresis prevents calibration drift after thermal cycling-critical for mission-critical navigation accuracy. | Use Scenario: 7½-digit DVM requiring 10V reference with <0.1ppm/°C effective TC and <1µVP-P noise in 0.1–10Hz band. IC Role / Device Role / Timing Role: Master reference for internal DAC and auto-zero circuits, isolated via Kelvin connections. Use Value: GND pin's low current (~1mA) enables true Kelvin sensing-reducing lead resistance errors to <0.1µV at 10mA load. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar precision voltage reference applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADR441BRZ | 10V output, 3ppm/°C max TC, 0.02% initial accuracy; higher cost, lower noise (3.5µVRMS), but requires ≥2V headroom. | Better TC and noise for metrology-grade instruments; not pin-compatible-requires layout change. | Select ADR441BRZ when TC <5ppm/°C is mandatory and board space allows SO-8 redesign. |
| REF5010AIDR | 10V output, 3ppm/°C max TC, 0.02% initial accuracy; integrated enable pin, 1.2mA quiescent current vs. 1.7mA. | Lower power for battery-operated DMMs; different pinout (SO-8 but VOUT/GND swapped)-not drop-in. | Choose REF5010AIDR for portable equipment needing enable control and <1.5mA supply current. |
Compared with LT1236CCS8-10#PBF, ADR441BRZ offers tighter TC and noise but demands more input headroom and new layout, while REF5010AIDR provides enable functionality and lower quiescent current at the cost of non-compatible pinout-making LT1236CCS8-10#PBF optimal for cost-sensitive, drop-in upgrades of legacy AD586-based systems.
Availability
LT1236CCS8-10#PBF is available at Aetrix Electronics and suitable for high-precision data acquisition, inertial navigation systems, and digital voltmeter designs requiring stable component supply with guaranteed long-term availability and traceable sourcing.
Supply support for LT1236CCS8-10#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The LT1236 family was developed by Linear Technology (acquired by ADI in 2017) to deliver ultra-stable, low-noise voltage references for metrology and precision instrumentation-leveraging buried zener technology to surpass bandgap performance without heater power.
FAQ
What is the maximum load current LT1236CCS8-10#PBF can source or sink while maintaining regulation?
LT1236CCS8-10#PBF can source or sink up to ±10mA while maintaining specified line and load regulation. At 10mA sourcing, output voltage changes by ≤250µV (25ppm/mA); sinking 10mA induces ≤1mV shift (100ppm/mA). Exceeding 10mA risks loss of regulation or thermal shutdown-external boost transistors are recommended for >10mA loads.
Can LT1236CCS8-10#PBF operate as a two-terminal shunt reference, and what is the minimum current required?
Yes, LT1236CCS8-10#PBF supports shunt mode operation with VIN open. In this configuration, it requires a minimum shunt current of 1.5mA to maintain regulation-verified across 0°C to 70°C. The device exhibits 50–150ppm/mA shunt load regulation, making it suitable for precision shunt regulator applications where input voltage varies widely.
What is the purpose of the TRIM pin on LT1236CCS8-10#PBF, and how is it used?
The TRIM pin (Pin 5) on LT1236CCS8-10#PBF enables fine adjustment of the 10V output with 70:1 attenuation and 12kΩ input impedance. A 10kΩ potentiometer between VOUT and GND yields ±10mV trim range. For the "C" grade, full ±0.7% adjustment is supported; trimming affects TC by <1ppm/°C when using low-impedance drive (<3kΩ), preserving long-term stability.
How does LT1236CCS8-10#PBF compare to bandgap references in terms of long-term stability and noise?
LT1236CCS8-10#PBF achieves 30ppm/1000hrs long-term stability and <6µVP-P (0.1–10Hz) noise-significantly better than typical bandgap references (e.g., 50–100ppm/1000hrs, >10µVP-P). This results from its buried zener structure, which eliminates surface degradation mechanisms and thermoelectric noise sources inherent in bandgap topologies.
Is LT1236CCS8-10#PBF pin-compatible with AD586 or AD587, and what does that mean for design migration?
Yes, LT1236CCS8-10#PBF is pin-compatible with AD586 and AD587 in SO-8 packages-same VIN, GND, VOUT, and TRIM pin locations. This allows direct replacement in existing layouts without PCB modification, enabling immediate performance upgrades (lower TC, noise, and hysteresis) while retaining legacy design validation and qualification.
LT1236CCS8-10#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Active
- Reference Type:
- Series, Shunt, Buried Zener
- Output Type:
- Fixed
- Voltage - Output (Min/Fixed):
- 10V
- Voltage - Output (Max):
- -
- Current - Output:
- 10 mA
- Tolerance:
- ±0.1%
- Temperature Coefficient:
- 15ppm/°C
- Noise - 0.1Hz to 10Hz:
- 6µVp-p
- Noise - 10Hz to 10kHz:
- 3.5µVrms
- Voltage - Input:
- 11.5V ~ 40V
- Current - Supply:
- 2mA
- Current - Cathode:
- 1.7 mA
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SO
LT1236CCS8-10#PBF FAQ
1.How can I place an order for LT1236CCS8-10#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LT1236CCS8-10#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LT1236CCS8-10#PBF reliable?
The price and inventory of LT1236CCS8-10#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LT1236CCS8-10#PBF is usually 5 days.
3.What payment methods are accepted for LT1236CCS8-10#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LT1236CCS8-10#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LT1236CCS8-10#PBF?
LT1236CCS8-10#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LT1236CCS8-10#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LT1236CCS8-10#PBF?
For technical support, including LT1236CCS8-10#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LT1236CCS8-10#PBF requirements.
6.How does Aetrix verify that LT1236CCS8-10#PBF is sourced from the original manufacturer or authorized distributors?
All LT1236CCS8-10#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LT1236CCS8-10#PBF meets industry standards.
7.What is the process for return or replacement of LT1236CCS8-10#PBF?
All LT1236CCS8-10#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LT1236CCS8-10#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LT1236CCS8-10#PBF part is unused and in its original packaging.
Return procedure for LT1236CCS8-10#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LT1236CCS8-10#PBF Tags
-
TL431AIDBZR
Texas Instruments
-
TL431BQDBZR
Texas Instruments

-
AN431AN-ATRG1
Diodes Incorporated

-
LM4040CYM3-2.5-TR
Microchip Technology

-
LM4040CYM3-4.1-TR
Microchip Technology
-
LM4040EIM3-2.5/NOPB
Texas Instruments

-
AZ431LBNTR-G1
Diodes Incorporated
-
LM4040D20IDBZR
Texas Instruments
-
LM4041DIM3-ADJ/NOPB
Texas Instruments
-
LM4040DIM3X-2.5/NOPB
Texas Instruments
-
LM4040DIM3-2.5/NOPB
Texas Instruments

-
AZ431LANTR-G1
Diodes Incorporated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

