Analog Devices Inc. LT1339CSW#TRPBF
- Part No.:
- LT1339CSW#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 20-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
LT1339CSW#TRPBF.pdf
- Description:
- IC REG CTLR BST/FWRD CONV 20SOIC
- Quantity:
- Payment:

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Product details
Overview
LT1339CSW#TRPBF from Analog Devices (formerly Linear Technology) is a high-power synchronous current-mode DC/DC controller IC designed for buck, inverting, and negative-output converters up to 60V input. It drives dual N-channel MOSFETs with adaptive nonoverlapping gate drive, supports programmable average current limiting (120 mV threshold), 150 kHz synchronizable oscillator, and 5 V reference output with 10 mA load capability - enabling robust 20 A, 28 V-to-5 V power conversion in telecom and industrial systems.
For engineers reviewing the LT1339CSW#TRPBF datasheet, LT1339CSW#TRPBF pinout, LT1339CSW#TRPBF application, or LT1339CSW#TRPBF equivalent, key selection considerations include its 20-pin SO Wide (SW) package, dual N-FET drive capability, average current limit programming via IAVG pin, soft-start control via SS pin, and phase-reversal support for topology flexibility.
Technical Context
The LT1339CSW#TRPBF implements a constant-frequency current-mode control architecture with internal transconductance error amplifier (gm = 1200–3200 µmho), programmable slope compensation via SL/ADJ pin, and minimum off-time protection (~1 µs). Its oscillator uses CT pin timing with RCT/CCT network and supports external synchronization up to 150 kHz.
It integrates dual gate drivers with adaptive dead-time control, undervoltage lockout (UVLO: 8.2–9.75 V falling, 200–350 mV hysteresis), precision RUN/SHDN shutdown threshold (1.15–1.35 V), and separate small-signal (SGND) and power (PGND) ground pins to minimize noise coupling in high-current switching applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | Up to 60 V on TS and SENSE+/- pins; 12VIN supply range: –0.3 V to 20 V - enables direct interface with high-voltage bus rails. |
| Switching Frequency | Programmable 150 kHz max, synchronizable - supports EMI-controlled designs and multi-phase coordination. |
| Average Current Limit Threshold | 120 mV across sense resistor (typical), set via external capacitor on IAVG pin - provides stable DC load current regulation independent of duty cycle. |
| 5 V Reference Output | 4.75–5.25 V (line/load/temp), 10 mA DC capable - powers external bias circuitry without auxiliary LDO. |
| Error Amplifier Reference | 1.242–1.258 V at VFB pin - sets output voltage accuracy in feedback loop (e.g., VOUT = 1.25 × (1 + R2/R1)). |
| Gate Drive Capability | Drives up to 10,000 pF total gate capacitance; TG/BG outputs swing 11.0–12.0 V (on), <0.7 V (off) - supports high-side/lower-side N-MOSFETs with low RDS(on). |
| Operating Temperature | 0°C to 70°C (C-grade) - validated for commercial industrial environments including telecom power shelves. |
Pinout & Package
LT1339CSW#TRPBF is housed in a 20-lead plastic SO Wide (SW) package (JEDEC MS-013AC), 7.6 mm × 15.4 mm body, 1.27 mm pitch, with exposed thermal pad (not electrically connected). Pin 1 is SYNC; pin 20 is VBOOST. SGND and PGND are separate pins to isolate analog and power return paths.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SYNC (1) | Oscillator synchronization input | TTL-compatible rising-edge trigger; enables master-slave frequency alignment without jitter accumulation. |
| 5VREF (2) | 5 V regulated output | Stable local supply for external logic or bias; disabled during shutdown - prevents unintended circuit activation. |
| CT (3) | Oscillator timing node | Connects to RCT pull-up and CCT capacitor; defines free-run frequency and sync response bandwidth. |
| SL/ADJ (4) | Slope compensation adjustment | Resistive loading tailors ramp compensation for >50% duty cycles - prevents subharmonic oscillation in boost/inverting topologies. |
| IAVG (5) | Average current limit integrator | 50 kΩ internal impedance + external capacitor sets averaging pole - rejects ripple, enabling true DC current limiting. |
| SS (6) | Soft-start timing input | 8 µA constant current charges external capacitor - linearly ramps VC clamp voltage to prevent inrush current. |
| VC (7) | Error amplifier output | Transconductance amplifier output; RC compensation here sets loop stability and transient response. |
| SGND (8) | Small-signal ground | Reference for VFB, VREF, CT, SL/ADJ - must be star-connected to minimize noise injection into feedback path. |
| VFB (9) | Error amplifier inverting input | Receives resistor-divider feedback; 0.5 µA bias current requires Thevenin resistance <5 kΩ for <0.5% error. |
| VREF (10) | Bandgap reference decoupling | 0.1 µF bypass to SGND stabilizes internal 1.25 V reference - critical for output voltage accuracy. |
| SENSE+ (11) | Current sense amplifier inverting input | Connects to high-side of sense resistor - common-mode range extends to 60 V for high-side sensing. |
| SENSE– (12) | Current sense amplifier noninverting input | Connects to low-side of sense resistor - differential input rejects common-mode noise in noisy power grounds. |
| RUN/SHDN (13) | Shutdown enable with UVLO | 1.25 V threshold with 25 mV hysteresis - supports both digital shutdown and analog input supply monitoring. |
| PHASE (14) | Topology configuration control | Floating = buck; grounded = inverting/boost - reconfigures TG/BG driver roles without PCB change. |
| PGND (15) | Power ground | Return for BG driver and internal power circuits - must connect directly to VIN bulk capacitor negative terminal. |
| BG (16) | Bottom gate driver output | Drives N-MOSFET source-connected to PGND - active-low during synchronous rectification. |
| 12VIN (17) | Main supply input | Powers internal circuitry and bootstrap charge pump - requires ≥1 µF ceramic bypass to PGND. |
| TS (18) | Topside switch node reference | Connects to source of high-side FET and bootstrap capacitor - withstands full switch-node dv/dt. |
| TG (19) | Top gate driver output | Drives N-MOSFET gate referenced to TS - bootstrapped operation enables high-side N-FET use. |
| VBOOST (20) | Bootstrap supply input | Charged via Schottky diode from 12VIN when TS is low - sustains TG drive during high-side conduction. |
Key Features
| Feature | Design Value |
|---|---|
| Adaptive nonoverlapping gate drive | Prevents shoot-through by dynamically adjusting dead time based on actual TG/BG voltage transitions - eliminates need for external timing resistors. |
| Programmable average current limit | 120 mV sense threshold with external IAVG capacitor - delivers precise DC current regulation unaffected by inductor ripple or duty cycle. |
| Phase reversal pin (PHASE) | Single-pin topology reconfiguration - enables buck, inverting, and negative-output converters using identical hardware layout. |
| 5 V reference with 10 mA drive | On-chip regulator powers external comparators, ADC references, or logic - reduces BOM count and improves system-level accuracy. |
| Minimum off-time protection | ~1 µs enforced minimum off period - ensures reliable bootstrap capacitor recharge and prevents main switch overstress during high-duty-cycle operation. |
Applications
| 48 V Telecom Power Supply | Industrial Control System PSU |
|---|---|
Use Scenario: Primary DC/DC stage converting –48 V or +48 V telecom battery backup to 5 V/12 V intermediate bus in shelf-mounted power modules. IC Role / Device Role / Timing Role: High-efficiency synchronous buck controller managing dual N-MOSFETs; PHASE pin grounded for inverting topology when fed from –48 V rail. Use Value: Delivers >90% efficiency at 20 A output while maintaining tight current limit accuracy across temperature - critical for N+1 redundant power architectures. |
Use Scenario: Field-programmable gate array (FPGA) or microcontroller core supply in PLC backplane, requiring precise 1.2 V or 1.8 V at up to 15 A with sequencing support. IC Role / Device Role / Timing Role: Current-mode controller with RUN/SHDN used for power-on sequencing; soft start prevents inrush into large downstream capacitors. Use Value: Programmable average current limit ensures safe startup under partial short-circuit conditions; 5 VREF powers FPGA configuration logic before core rail is enabled. |
| Lead-Acid Battery Backup System | Automotive Heavy Equipment DC/DC |
Use Scenario: Bidirectional converter in UPS systems charging 24 V lead-acid batteries from 48 V DC bus while providing regulated 12 V output during outage. IC Role / Device Role / Timing Role: Controller configured in buck-boost mode using PHASE pin control; average current limit protects battery during high-current charge phases. Use Value: 60 V absolute maximum rating on SENSE+/TS pins allows direct connection to battery terminals without level-shifting - simplifies fault detection and monitoring. |
Use Scenario: 24 V-to-5 V/3.3 V power conversion for engine control units (ECUs) or telematics modules in construction or agricultural vehicles. IC Role / Device Role / Timing Role: Synchronous buck controller operating from wide-input 12–36 V nominal bus; UVLO hysteresis prevents cycling during cranking transients. Use Value: Undervoltage lockout with 350 mV hysteresis ensures clean disable/enable during cold-cranking dips below 9 V - avoids brownout resets in safety-critical systems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-power synchronous DC/DC controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC3775 | Higher integration: includes MOSFET drivers with 2 A peak sink/source; supports up to 38 V VIN; no separate 5 VREF output. | Targeted at compact, high-density designs where board space is constrained; lacks dedicated 5 V bias rail for external circuitry. | Select LTC3775 when gate drive strength and footprint reduction outweigh need for integrated 5 V reference. |
| MP2918 | Lower voltage rating (36 V max); fixed 1.2 V reference (no 5 VREF); supports only buck topology; no PHASE pin for topology reversal. | Suitable for cost-sensitive 12 V/24 V automotive or industrial supplies where inverting operation is not required. | Choose MP2918 for simplified buck-only designs with tighter input voltage range and lower BOM cost. |
Compared with LTC3775 and MP2918, the LT1339CSW#TRPBF uniquely combines 60 V input tolerance, programmable average current limiting, topology-flexible PHASE control, and a standalone 5 V reference - making it optimal for high-reliability, multi-rail telecom and industrial power systems requiring design reuse across topologies.
Availability
LT1339CSW#TRPBF is available at Aetrix Electronics and suitable for 48 V telecom power supplies, industrial control system PSUs, and lead-acid battery backup systems requiring stable component supply and long-term lifecycle support.
Supply support for LT1339CSW#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and power management semiconductors, formed through the acquisition of Linear Technology in 2017.
The LT1339CSW#TRPBF belongs to ADI's legacy Linear Technology high-voltage power controller product line, engineered for rugged, high-efficiency DC/DC conversion in telecom infrastructure, industrial automation, and transportation systems.
FAQ
What is the maximum input voltage supported by the LT1339CSW#TRPBF?
The LT1339CSW#TRPBF supports up to 60 V on its TS, SENSE+, and SENSE– pins, and –0.3 V to 20 V on the 12VIN supply pin. This enables direct interface with 48 V telecom buses and industrial 24–60 V rails. Absolute maximum ratings must not be exceeded; sustained operation above 60 V risks permanent damage to the LT1339CSW#TRPBF.
How does the average current limit function work on the LT1339CSW#TRPBF?
The LT1339CSW#TRPBF implements average current limiting via the IAVG pin, which connects to an internal 50 kΩ impedance and external capacitor forming a low-pass filter. When the averaged sense amplifier output exceeds 120 mV, the current comparator threshold is clamped - ensuring precise DC load current regulation independent of inductor ripple. Shorting IAVG to SGND disables this feature.
Can the LT1339CSW#TRPBF be used in inverting or negative-output configurations?
Yes - the LT1339CSW#TRPBF supports inverting and negative-output topologies via its PHASE pin (Pin 14). Grounding PHASE reverses the roles of TG and BG drivers, enabling the IC to drive high-side and low-side switches in configurations such as inverting buck-boost. This functionality is confirmed in the LT1339CSW#TRPBF datasheet Figure 1 and Applications Information section.
What is the purpose of the 5 V reference (5VREF) pin on the LT1339CSW#TRPBF?
The 5VREF pin on the LT1339CSW#TRPBF provides a regulated 4.75–5.25 V output capable of sourcing up to 10 mA DC. It powers external circuitry such as level translators, comparators, or microcontroller peripherals, eliminating the need for a separate LDO. The LT1339CSW#TRPBF disables 5VREF during shutdown, preventing unintended activation of downstream components.
How is soft start controlled on the LT1339CSW#TRPBF?
Soft start on the LT1339CSW#TRPBF is implemented via the SS pin (Pin 6), which sources a constant 8 µA current into an external capacitor. As the capacitor voltage ramps, it controls the VC pin clamp level - gradually increasing the current limit and enabling smooth output voltage rise. The LT1339CSW#TRPBF also resets the SS capacitor during UVLO or shutdown, ensuring graceful recovery.
LT1339CSW#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 20-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Output Type:
- Transistor Driver
- Function:
- Step-Up, Step-Up/Step-Down
- Output Configuration:
- Positive, Isolation Capable
- Topology:
- Boost, Forward Converter
- Number of Outputs:
- 1
- Output Phases:
- 1
- Voltage - Supply (Vcc/Vdd):
- Up to 20V
- Frequency - Switching:
- -
- Duty Cycle (Max):
- 90%
- Synchronous Rectifier:
- No
- Clock Sync:
- Yes
- Serial Interfaces:
- -
- Control Features:
- Current Limit, Enable, Phase Control, Soft Start
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-SO
LT1339CSW#TRPBF FAQ
1.How can I place an order for LT1339CSW#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LT1339CSW#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LT1339CSW#TRPBF reliable?
The price and inventory of LT1339CSW#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LT1339CSW#TRPBF is usually 5 days.
3.What payment methods are accepted for LT1339CSW#TRPBF?
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4.How is shipping managed for LT1339CSW#TRPBF?
LT1339CSW#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LT1339CSW#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LT1339CSW#TRPBF?
For technical support, including LT1339CSW#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LT1339CSW#TRPBF requirements.
6.How does Aetrix verify that LT1339CSW#TRPBF is sourced from the original manufacturer or authorized distributors?
All LT1339CSW#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LT1339CSW#TRPBF meets industry standards.
7.What is the process for return or replacement of LT1339CSW#TRPBF?
All LT1339CSW#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LT1339CSW#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LT1339CSW#TRPBF part is unused and in its original packaging.
Return procedure for LT1339CSW#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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