Analog Devices Inc. LT1468CDD#PBF
- Part No.:
- LT1468CDD#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 8-WFDFN Exposed Pad
- Datasheet:
-
LT1468CDD#PBF.pdf
- Description:
- IC OPAMP GP 1 CIRCUIT 8DFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LT1468CDD#PBF from Analog Devices (formerly Linear Technology) is a precision high-speed operational amplifier optimized for 16-bit data acquisition systems, featuring 90 MHz gain bandwidth, 22 V/µs slew rate, and 900 ns settling time to 150 µV for 10 V steps. Its complementary bipolar process delivers low distortion (–96.5 dB THD at 100 kHz), 5 nV/√Hz input voltage noise, and tailored input bias current matching for inverting DAC I-to-V conversion.
For engineers reviewing the LT1468CDD#PBF datasheet, LT1468CDD#PBF pinout, LT1468CDD#PBF application, or LT1468CDD#PBF equivalent, key selection criteria include DC accuracy (75 µV max VOS, 2 µV/°C drift), AC performance (full-power bandwidth up to 350 kHz at ±15 V), output drive capability (±12.8 V into 2 kΩ), and DFN-8 package thermal performance (θJA = 43°C/W).
Technical Context
The LT1468CDD#PBF employs a single-stage complementary bipolar architecture with factory-trimmed inverting input bias current cancellation, enabling superior DC accuracy in current-to-voltage conversion. Its 90 MHz gain bandwidth ensures >100 dB open-loop gain at 100 kHz, reducing harmonic distortion in ADC buffer and active filter applications.
Designed for ±5 V and ±15 V dual supplies, it achieves unity-gain stability while maintaining 16-bit settling performance across temperature (0°C to 70°C operating range). The exposed-pad DFN-8 package provides low thermal resistance and supports high-frequency layout integrity via controlled impedance routing and RF-quality bypassing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Gain Bandwidth | 90 MHz at ±15 V - enables >100 dB loop gain at 100 kHz for low-distortion signal conditioning |
| Slew Rate | 22 V/µs at ±15 V - supports full-scale 10 V step response within 450 ns, critical for fast DAC settling |
| Settling Time | 900 ns to 150 µV (AV = –1, 10 V step) - meets 16-bit (150 µV = 1 LSB @ 10 V) accuracy requirements |
| Input Offset Voltage | 75 µV max at ±15 V - ensures <0.75 LSB error in 16-bit systems with 10 V full scale |
| THD + Noise | –96.5 dB at 100 kHz, 10 VP-P - preserves signal fidelity in audio and instrumentation bandpass filters |
| Input Noise Density | 5 nV/√Hz voltage noise + 0.6 pA/√Hz current noise - optimized for source impedances 1 kΩ–20 kΩ |
| Output Swing | ±12.8 V into 2 kΩ at ±15 V - delivers rail-to-rail usable dynamic range for ±12 V systems |
Pinout & Package
LT1468CDD#PBF uses an 8-lead (3 mm × 3 mm) plastic DFN package with exposed thermal pad internally connected to V–. Pin 8 (NULL) is factory-trimmed and must remain unconnected.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (NULL) | Inverting input bias current trim node | Factory-adjusted; no external connection permitted - floating pin avoids leakage-induced offset drift |
| 2 (–IN) | Inverting input | Low-bias-current input (≤10 nA) optimized for precision I-to-V conversion with matched feedback networks |
| 3 (+IN) | Noninverting input | Untrimmed input; requires asymmetric source impedance to avoid degrading DC accuracy |
| 4 (V–) | Negative supply | Internally connects to exposed thermal pad - mandatory soldering for thermal performance and EMI suppression |
| 5 (DNC*) | Do-not-connect terminal | No internal connection; must be left floating - prevents parasitic coupling in high-speed layouts |
| 6 (V+) | Positive supply | Accepts ±5 V to ±15 V dual supplies; PSRR ≥100 dB minimizes supply ripple injection |
| 7 (OUT) | Amplifier output | Capable of driving 2 kΩ loads to ±12.8 V; stable with ≤100 pF capacitive load in unity gain |
| 8 (NULL) | Inverting input bias current trim node | Identical function to Pin 1 - both are factory-trimmed and must remain unconnected |
Key Features
| Feature | Design Value |
|---|---|
| 16-bit accurate settling | 900 ns to 150 µV ensures full resolution in high-speed DAC I-to-V converters without post-processing correction |
| Optimized input bias cancellation | Inverting input bias current trimmed to ≤10 nA at 0 V common-mode - eliminates resistor-matching requirement in transimpedance amps |
| Total input noise optimization | Minimum integrated noise in 1 kΩ–20 kΩ source range - maximizes SNR in photodiode and sensor front-ends |
| High open-loop gain at frequency | 90 MHz GBW sustains >1000 V/mV gain at 100 kHz - reduces harmonic distortion in ADC buffers and active filters |
| Thermally enhanced DFN package | θJA = 43°C/W with exposed V– pad - enables continuous operation at full output swing without derating |
Applications
| 16-Bit DAC I-to-V Converter | Precision Instrumentation Amplifier |
|---|---|
Use Scenario: Converting 16-bit current-output DAC (e.g., LTC1597) into precise voltage with minimal settling error. IC Role / Device Role / Timing Role: Transimpedance amplifier with gain-setting feedback network and 20 pF compensation capacitor. Use Value: Achieves 1.7 µs settling to 16-bit accuracy (150 µV), outperforming prior-generation op amps in DAC output stage speed and linearity. | Use Scenario: Building 3-op-amp instrumentation amplifier for microvolt-level sensor signals in medical or test equipment. IC Role / Device Role / Timing Role: High-gain, low-drift output stage amplifying differential signal after initial gain and filtering. Use Value: Delivers <0.001% gain nonlinearity and –96.5 dB THD at 100 kHz, preserving signal integrity in narrowband physiological measurements. |
| ADC Buffer | Low Distortion Active Filter |
Use Scenario: Driving sample-and-hold input of 16-bit ADC (e.g., LTC1605) with minimal loading and distortion. IC Role / Device Role / Timing Role: Unity-gain buffer isolating high-impedance signal sources from ADC input capacitance. Use Value: Maintains full 16-bit AC/DC accuracy (±75 µV offset, –96.5 dB THD) while supporting 100 ksps sampling without aperture jitter degradation. | Use Scenario: Implementing 100 kHz bandpass filter for signal generator cleanup or communications channel conditioning. IC Role / Device Role / Timing Role: High-Q active filter stage using Sallen-Key or multiple-feedback topology. Use Value: Enables –106 dB second-harmonic distortion at 1 VRMS, meeting spectral purity requirements for calibration-grade test equipment. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar precision high-speed op amp applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LT1469CS8#PBF | Dual-channel version in SO-8; identical AC/DC specs but higher supply current (6.5 mA per amp vs 5.2 mA) | Preferred for space-constrained dual-path systems (e.g., differential ADC drivers); not suitable for single-channel footprint replacement | Select when dual amplifiers are needed and board area permits SO-8 mounting; verify thermal dissipation with doubled ICC |
| LT1800CS8#PBF | Lower power (1.6 mA), rail-to-rail output, reduced GBW (80 MHz), lower slew rate (25 V/µs), higher VOS (350 µV max) | Better suited for battery-powered ±5 V systems where 14-bit accuracy suffices; cannot meet 16-bit settling or THD targets | Choose for low-voltage, low-power designs accepting trade-offs in precision and speed; not drop-in for LT1468CDD#PBF's 16-bit role |
Compared with LT1468CDD#PBF, LT1469CS8#PBF offers dual-channel integration at the cost of higher quiescent power, while LT1800CS8#PBF sacrifices 16-bit accuracy and 90 MHz bandwidth for rail-to-rail operation and sub-2 mA supply current - making LT1468CDD#PBF uniquely balanced for high-resolution, high-speed analog signal chains.
Availability
LT1468CDD#PBF is available at Aetrix Electronics and suitable for high-accuracy data acquisition, precision instrumentation, and low-distortion active filter applications requiring stable component supply across industrial and test equipment lifecycles.
Supply support for LT1468CDD#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies for precision measurement and control.
The LT1468 product line was designed specifically for 16-bit data converter interface applications, combining high DC accuracy with wide bandwidth to eliminate the traditional trade-off between resolution and speed in precision op amps.
FAQ
What is the maximum input offset voltage specification for LT1468CDD#PBF at ±15 V supply?
The maximum input offset voltage for LT1468CDD#PBF is 75 µV at ±15 V supply and 25°C, with a maximum drift of 2 µV/°C over the 0°C to 70°C operating range. This ensures <0.75 LSB error in 16-bit systems with 10 V full-scale range, directly supporting precision DAC I-to-V and ADC buffer applications where DC accuracy is critical. The LT1468CDD#PBF maintains this specification across its specified temperature range without requiring external trimming.
Can LT1468CDD#PBF drive capacitive loads, and what is the recommended compensation for 100 pF?
Yes, LT1468CDD#PBF can drive up to 100 pF in unity-gain configuration and up to 300 pF in inverting gain-of–1 configuration. For 100 pF loads in unity gain, Linear Technology recommends adding a small series resistor (typically 10–50 Ω) between the output and load, plus a feedback capacitor (CF) from output to inverting input. The value should satisfy CF ≥ CIN (4 pF typical), so ≥5 pF is appropriate. This prevents peaking and ensures stable step response without sacrificing 16-bit settling performance in the LT1468CDD#PBF.
What is the thermal resistance (θJA) of LT1468CDD#PBF, and how does the exposed pad affect thermal performance?
The junction-to-ambient thermal resistance (θJA) of LT1468CDD#PBF is 43°C/W when mounted on a standard 2-layer PCB with the exposed thermal pad fully soldered to a 1-inch² copper plane. The exposed pad is internally connected to V–, so proper soldering provides both low-thermal-resistance heat transfer and improved EMI immunity. Without pad connection, θJA degrades significantly - ensuring robust thermal design for continuous ±12.8 V output swing into 2 kΩ loads in the LT1468CDD#PBF.
How does LT1468CDD#PBF achieve 16-bit settling performance, and what is the measured settling time to 150 µV?
LT1468CDD#PBF achieves 16-bit settling through a single-stage complementary bipolar architecture with optimized thermal layout and factory-trimmed input bias current cancellation. Its measured settling time to 150 µV (1 LSB at 10 V full scale) is 900 ns for a 10 V step in inverting configuration (AV = –1) at ±15 V supply. This result is verified per AN74 methodology using differential measurement and 100× clamped gain, confirming the LT1468CDD#PBF meets true 16-bit timing accuracy without post-processing.
Is pin 8 of LT1468CDD#PBF functional, and what happens if it is connected externally?
No, pin 8 of LT1468CDD#PBF is a factory-trimmed NULL terminal for inverting input bias current adjustment and must remain unconnected. External connection introduces leakage paths and thermal gradients that degrade offset voltage stability and increase drift - violating the device's 2 µV/°C spec. The datasheet explicitly states "DO NOT CONNECT" for both pin 1 and pin 8, and connecting either compromises the LT1468CDD#PBF's 16-bit DC accuracy and long-term reliability in precision applications.
LT1468CDD#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 8-WFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Amplifier Type:
- General Purpose
- Number of Circuits:
- 1
- Output Type:
- -
- Slew Rate:
- 22V/µs
- Gain Bandwidth Product:
- 90 MHz
- -3db Bandwidth:
- -
- Current - Input Bias:
- 10 nA
- Voltage - Input Offset:
- 100 µV
- Current - Supply:
- 3.9mA
- Current - Output / Channel:
- 22 mA
- Voltage - Supply Span (Min):
- 9 V
- Voltage - Supply Span (Max):
- 30 V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-DFN (3x3)
LT1468CDD#PBF FAQ
1.How can I place an order for LT1468CDD#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LT1468CDD#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LT1468CDD#PBF reliable?
The price and inventory of LT1468CDD#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LT1468CDD#PBF is usually 5 days.
3.What payment methods are accepted for LT1468CDD#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LT1468CDD#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LT1468CDD#PBF?
LT1468CDD#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LT1468CDD#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LT1468CDD#PBF?
For technical support, including LT1468CDD#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LT1468CDD#PBF requirements.
6.How does Aetrix verify that LT1468CDD#PBF is sourced from the original manufacturer or authorized distributors?
All LT1468CDD#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LT1468CDD#PBF meets industry standards.
7.What is the process for return or replacement of LT1468CDD#PBF?
All LT1468CDD#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LT1468CDD#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LT1468CDD#PBF part is unused and in its original packaging.
Return procedure for LT1468CDD#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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